A 1280x960 3.75um pixel CMOS imager with Triple Exposure HDR

Abstract

A triple exposure 20-bit output high dynamic range (HDR) CMOS imager with sub 2e- rms noise floor is presented. The array consists of 1280x960 pinned photodiode pixels with 3.75um pitch and programmable (high or low) conversion gain (Fig.1). A two-way row sharing architecture is utilized after weighing fill factor (i.e. quantum efficiency and crosstalk) against conversion gain (reduced with sharing). The dual conversion gain (CG) feature allows CG adjustment globally across all pixels to match the overall light level in the scene. This is controlled by turning the DCG gate ON or OFF to connect or disconnect the in-pixel capacitor C to the floating diffusion (FD) node. CG is equal to 147uV/e- in High CG (HCG) mode and 37uV/e- in Low CG (LCG) mode. Fig.2 illustrates the pixel readout timing in LCG mode. The DCG gate is turned on when ROW is active, as well as during the extra pixel reset operation. The latter is done to avoid long duty cycle high voltage stress on node A when the sensor is running in LCG mode.