A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance

Abstract

1Mb embedded STT-MRAM macro using 45nm CMOS process includes two key design features; a dual-voltage row decoder with a charge sharing scheme for read operations and a sensing circuit with two equalizers and read-disturbance-free reference cells. These designs minimize read-disturbance and achieve fast read operation. © 2011 JSAP (Japan Society of Applied Physi.