A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8MHz signal bandwidth and consumes 4.3mW. © 2011 JSAP (Japan Society of Applied Physi.
CITATION STYLE
Rao, S., Young, B., Elshazly, A., Yin, W., Sasidhar, N., & Hanumolu, P. K. (2011). A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 270–271).
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