NetFPGA - An Open Platform for Gigabit-rate Network Switching and Routing John W. Lockwood, Nick McKeown, Greg Watson, Glen Gibb, Paul Hartke, Jad Naous, Ramanan Raghuraman, and Jianying Luo Stanford University ��� Computer Systems Laboratory: Gates 3A-337, Stanford, CA 94305-9030 {jwlockwd, nickm, gwatson, grg, phartke, jnaous, ramananr, jyluo}@stanford.edu Abstract The NetFPGA platform enables students and researchers to build high-performance networking systems in hardware. A new version of the NetFPGA platform has been devel- oped and is available for use by the academic community. The NetFPGA 2.1 platform now has interfaces that can be parameterized, therefore enabling development of modular hardware designs with varied word sizes. It also includes more logic and faster memory than the previous platform. Field Programmable Gate Array (FPGA) logic is used to implement the core data processing functions while soft- ware running on embedded cores within the FPGA and/or programs running on an attached host computer implement only control functions. Reference designs and component libraries have been developed for the CS344 course at Stan- ford University. Open-source Verilog code is available for download from the project website. 1 Introduction Hardware-accelerated network switches and routers en- abled rapid growth of the Internet. Today, Gigabit Ethernet switches are widely deployed to switch traffic within Lo- cal Area Networks (LANs) and route Internet Protocol (IP) packets across Wide Area Networks (WANs). Commer- cial vendors use Application Specific Integrated Circuits (ASICs) and/or Field Programmable Gate Arrays (FPGAs) to accelerate the switching, routing, and processing of net- work data. Today���s students must understand how to pro- cess packets in hardware if they wish to build real systems. At most universities, students build network systems us- ing software. Most hands-on courses only teach how to ���This research is supported by gifts from Xilinx, Agilent, Micron, Broadcom, and Cisco as well as grants from NSF EIA-0305729 and CNS- 0551703. Any opinions, findings, conclusions, or recommendations ex- pressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation or other sponsors of this project. write software programs that send and receive packets from user-space sockets. Advanced courses typically only cover methods that interface software to the kernel of an operat- ing system. While software-based systems can process a limited volume of network traffic, they are not suitable for switching, routing, and processing large volumes of packets that appear on a fully-loaded Gigabit Ethernet links. 2 The NetFPGA Platform The NetFPGA 2.1 platform contains a large Xilinx Virtex-II Pro FPGA that is programmed with user-defined logic and a small Xilinx Spartan FPGA that programs the Virtex and implements the PCI interface to a host proces- sor. The platform includes two Static RAMs (SRAMs) that operate synchronously with the FPGA and two second- generation Double Date Rate (DDR2) SDRAM devices that operate asynchronously with the FPGA. A quad-port physical-layer transceiver (PHY) is provided enabling the platform to send and receive packets over four, standard twisted-pair Ethernet cables. Two Serial ATA (SATA) con- nectors on the platform allow multiple NetFPGAs within a system to exchange data at high speeds. A photograph of the NetFPGA 2.1 platform is shown in Figure 1. Figure 1. Photo of the NetFPGA 2.1 The NetFPGA library of logic includes a Verilog skele- ton design that instantiates four Gigabit Ethernet Media Ac- cess Controllers (GMACs) and interfaces the logic to the SRAM and DDR2 memory. Internal module interfaces use a standard request-grant First-In-First-Out (FIFO) protocol. 1