INSTITUTE OF PHYSICS PUBLISHING JOURNAL OF PHYSICS D: APPLIED PHYSICS J. Phys. D: Appl. Phys. 39 (2006) R387���R406 doi:10.1088/0022-3727/39/21/R01 TOPICAL REVIEW Semiconductor nanowires Wei Lu1,4 and Charles M Lieber2,3 1 Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109, USA 2 Department of Chemistry and Chemical Biology, Harvard University, Cambridge, MA 02138, USA 3 Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138, USA E-mail: wluee@umich.edu Received 6 June 2006 Published 20 October 2006 Online at stacks.iop.org/JPhysD/39/R387 Abstract Semiconductor nanowires (NWs) represent a unique system for exploring phenomena at the nanoscale and are also expected to play a critical role in future electronic and optoelectronic devices. Here we review recent advances in growth, characterization, assembly and integration of chemically synthesized, atomic scale semiconductor NWs. We first introduce a general scheme based on a metal-cluster catalyzed vapour���liquid���solid growth mechanism for the synthesis of a broad range of NWs and nanowire heterostructures with precisely controlled chemical composition and physical dimension. Such controlled growth in turn results in controlled electrical and optical properties. Subsequently, we discuss novel properties associated with these one-dimensional (1D) structures such as discrete 1D subbands formation and Coulomb blockade effects as well as ballistic transport and many-body phenomena. Room-temperature high-performance electrical and optical devices will then be discussed at the single- or few-nanowire level. We will then explore methods to assemble and integrate NWs into large-scale functional circuits and real-world applications, examples including high-performance DC/RF circuits and flexible electronics. Prospects of a fundamentally different ���bottom-up��� paradigm, in which functionalities are coded during growth and circuits are formed via self-assembly, will also be briefly discussed. (Some figures in this article are in colour only in the electronic version) 1. Introduction Great advances in integrated circuit technologies have been accomplished during the past four decades that resulted in electronic devices with higher device density, faster clock rate and lower power consumption [1]. However, as the devices reach deep sub-100 nm scale, conventional scaling methods which maintain the device���s basic structure while shrinking its size face increasing technological and fundamental challenges. For example, device size fluctuations will result in a large spread in device characteristics at the nanoscale, affecting key 4 Author to whom any correspondence should be addressed. parameters such as the threshold voltage and on/off current. Increasing demand on the resolution of the equipment and expenses of building and operating the facilities also pushes the traditional approach towards its practical limit and hinders device scaling from reaching true atomic level [2, 3]. To sustain the historical scaling trend beyond CMOS, novel one-dimensional (1D) structures, including carbon nanotubes (CNTs) and semiconductor nanowires (NWs), have been proposed as the active components (as well as interconnects) in future nanoscale devices and circuits. In this case, the critical device size is defined during the growth (chemical synthesis) process and can be controlled with atomic scale resolution. To date, great efforts and 0022-3727/06/210387+20$30.00 �� 2006 IOP Publishing Ltd Printed in the UK R387

Topical Review progress have been made in the field of CNTs, although CNT based applications are still hindered by difficulties to produce uniform, semiconducting nanotubes. On the other hand, semiconductor NWs can be prepared with reproducible electronic properties in high-yield, as required for large- scale integrated systems. Furthermore, the well-controlled NW growth process implies that materials with distinct chemical composition, structure, size and morphology can be integrated [5]. Such an ability to build specific functions into the system during growth may in turn lead to bottom-up assembly of integrated circuits [5], which offers the potential of parallel production of massive number of devices with similar material and electrical/optical properties. Drastically different from the ���top-down��� paradigm commonly used in today���s semiconductor industry, this ���bottom-up��� paradigm, analogous to the way that nature works, may prove to be a suitable solution to the technological challenges as devices approach atomic size. From a fundamental physics point of view, the low- dimensional nanowire structure is an ideal platform to probe properties which may be inaccessible or hard to achieve in larger devices, due to the reduced device size and ideal material properties. For example, discreteness of electrons comes into play when the Coulomb energy associated with the addition of an individual electron becomes larger than the thermal energy 1D quantum wires and zero-dimensional quantum dots (QDs) form when the relevant device size is comparable to the de Broglie wavelength of the carriers. As a result, the electrical and optical properties in these nanoscale devices are determined not only by the materials composition but can also be tailored by the specific device geometry. 2. Growth of NWs 2.1. The vapour���liquid���solid growth method Semiconductor NWs are generally synthesized by employing metal nanoclusters as catalysts via a vapour���liquid���solid (VLS) process (figure 1) [6]. In this process, the metal nanoclusters are heated above the eutectic temperature for the metal���semiconductor system of choice in the presence of a vapour-phase source of the semiconductor, resulting in a liquid droplet of the metal/semiconductor alloy. The continued feeding of the semiconductor reactant into the liquid droplet supersaturates the eutectic, leading to nucleation of the solid semiconductor. The solid���liquid interface forms the growth interface, which acts as a sink causing the continued semiconductor incorporation into the lattice and, thereby, the growth of the nanowire with the alloy droplet riding on the top. The gaseous semiconductor reactants can be generated through decomposition of precursors in a chemical vapour deposition (CVD) process or through momentum and energy transfer methods such as pulsed laser ablation [7] or molecular beam epitaxy (MBE) [8] from solid targets. So far, CVD has been the most popular technique. In CVD���VLS growth, the metal nanocluster serves as a catalyst at which site the gaseous precursor decompose, providing the gaseous semiconductor reactants. In the case of SiNW growth (figure 1), silane (SiH4) and Au nanoparticles are normally used as the precursor and catalysts, respectively. Besides group IV materials, compound (a) (b) Figure 1. Schematic of VLS growth of Si nanowires (SiNWs). (a) A liquid alloy droplet AuSi is first formed above the eutectic temperature (363 ���C) of Au and Si. The continued feeding of Si in the vapour phase into the liquid alloy causes oversaturation of the liquid alloy, resulting in nucleation and directional nanowire growth. (b) Binary phase diagram for Au and Si illustrating the thermodynamics of VLS growth. III���V and II���VI NWs have also been produced with the VLS method, in which pseudobinary phase diagrams for the catalyst and compound semiconductor of interest are employed. In the compound semiconductor case, metal-organic chemical vapour deposition (MOCVD) [9] or pulsed laser ablation [10] are typically used to provide the reactants. There are two competing interfaces during nanowire growth, the liquid/solid interface between the eutectic and the nanowire and the gas/solid interface between the reactants and the exposed surface of the growing nanowire. Precipitation through the first interface results in the VLS growth and axial elongation of the nanowire, while dissociative adsorption on the second interface results in vapour���solid growth and thickening in the radial direction. Either mechanism can be dominating in an actual growth process, depending on the detailed growth condition such as the pressure, flow rate, temperature, reactant species and background gases that are by-products of growth reactions. For example, in the above- mentioned SiNW growth process, low temperature growth can reduce the rate of direct thermal dissociation of silane hence, axial nanowire growth is favoured. Hydrogen has also been found to mitigate radial growth through suppression of either the adsorption of the reactants by terminating the Si surface [11] or of the dissociation of silane [12,13]. The use of H2 as the carrier gas also passivates the NW surface in a manner similar to that observed in thin-film growth [14] and reduces roughening along the NW. Uniform NWs with negligible diameter variation can thus be achieved through careful control of the growth conditions, including the employment of local heaters to reduce uncontrolled decomposition of silane [15]. On the other hand, tapered NWs are products from simultaneous growth in both the axial and radial directions R388

Topical Review Figure 2. (a) and (b) HRTEM images of SiNWs with diameters of 12.3 nm (a) and 3.5 nm (b). Sale bar: 5 nm. (c)���(e) Histogram of the growth directions for SiNWs with diameters from 3 to 10 nm (c), from 10 to 20 nm (d) and from 20 to 30 nm (e). Adapted from [11]. and are generally not desirable for most electrical and optical applications. In the CVD���VLS growth process the diameter of the nanowire is determined by that of the starting nanocluster, and uniform, atomic-scale NWs can be obtained in a well- controlledgrowthprocessasnanoclusterswithdiametersdown to a few nanometres are now commercially available. Wu et al reported growth of uniform SiNWs with diameters down to 3 nm [11] using SiH4 as the precursor and H2 as the carrier gas. Wu performed detailed high-resolution transmission electron micrography (HRTEM) studies on these SiNWs and observed that the NWs are single-crystalline with little or no visible amorphous oxide even at this scale. The resulting SiNWs show narrow size distributions of 13.2 �� 1.7 nm, 5.9 �� 1.1 nm, and 4.6 �� 1.2 nm, respectively when gold nanoclusters of diameters of 10 (9.7 �� 1.5) nm, 5 (4.9 �� 0.7) nm, and 2 (3.3 �� 1) nm are used. The increase in the NW diameters compared with those of the starting nanoclusters was attributed to the supersaturation of silicon in gold nanoclusters during the formation of the liquid droplet prior to nucleation, an effect observed previously with in situ observations of the growth of germanium NWs [16]. The crystallographic orientation of the NW during VLS growth is chosen to minimize the total free energy, as the process is thermodynamically driven. The total free energy includes the ���bulk��� energy of the SiNW, the Au/Si interface energy and the Si/vacuum interface energy. In Wu���s study, the growth directions of SiNWs with different diameters are carefully examined [11]. A histogram of the growth directions of the SiNWs is shown in figure 2. Prior studies of VLS growth on micrometre-scale silicon whiskers have shown that the growth is primarily along the 111 direction, since the solid���liquid interface parallel to a (111) plane possesses lowest Figure 3. (a) HRTEM image of the catalyst alloy/NW interface of a SiNW with a 111 growth axis. Scale bar: 20 nm. (b) HRTEM image of a catalyst alloy/NW interface of a SiNW with a 110 growth axis. Scale bar: 5 nm. (c) HRTEM cross-sectional image (scale bars: 5 nm) and (d) equilibrium shapes for the NW cross sections predicted by Wulff construction. Adapted from [11]. free-energy [6]. The predominant 111 growth direction (figure 2(e)) and the single (111) plane at the catalyst/NW interface (figure 3(a)) were indeed observed on VLS-grown SiNWs as well, with diameters larger than 20 nm [11]. On the other hand, 110 becomes the predominant growth direction for NWs with diameter smaller than 10 nm (figure 2(c)). This phenomenon can be explained by the fact that the Si/vacuum surface energy becomes increasingly dominating when the surface/volume ratio is increased as the nanowire diameter is decreased, as the Si/vacuum surfaces parallel to 111 axis consist of the lowest free-energy (111) and (100) planes (figures 3(c) and (d)). Interestingly, 110 growth does not arise from the formation of a liquid/solid (110) interface. As shown in figure 3(b), the catalyst/NW interface now consists of two low energy {111} planes, whereby the 111 and 11 ��� 1 directions combine to yield a growth axis of 110 . Such observations are consistent with the thermodynamic picture of the VLS growth mechanism. The 112 growth direction, which is observed for a substantial fraction of intermediate-diameter SiNWs (figure 2(d)), can be explained asa���transitional���directionbetweenthe 111 and 110 growth directions since the (112) plane is a stepped plane between the (111) and (110) planes [17]. 2.2. Nanowire heterostructures Compared with nanostructures fabricated from other ap- proaches such as vapour���solid growth [18] or solution based liquid���solid growth [19], the VLS process offers one key advantage���heterostructures can be achieved at the individual devicelevelinacontrolledfashion. Bothaxialheterostructures (figures 4(c) and (e)), in which sections of different materials with the same diameter are grown along the wire axis [20,21], and radial heterostructures (figures 4(d) and (f )), in which R389