A Survey of Research and Practices of Network-on-Chip TOBIAS BJERREGAARD AND SHANKAR MAHADEVAN Technical University of Denmark The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative. Categories and Subject Descriptors: A.1 [Introductory and Survey] B.4.3 [Input/Output and Data-Communications]: Interconnections B.7.1 [Integrated Circuits]: Types and Design Styles C.5.4 [Computer System Implementation]: VLSI Systems C.2.1 [Computer-Communication Networks]: Network Architecture and Design C.0 [General]: System Architectures General Terms: Design Additional Key Words and Phrases: Chip-area networks, communication-centric design, communication abstractions, GALS, GSI design, interconnects, network-on-chip, NoC, OCP, on-chip communication, SoC, sockets, system-on-chip, ULSI design 1. INTRODUCTION Chip design has four distinct aspects: computation, memory, communication, and I/O. As processing power has increased and data intensive applications have emerged, the challenge of the communication aspect in single-chip systems, Systems-on-Chip (SoC), has attracted increasing attention. This survey treats a prominent concept for commu- nication in SoC known as Network-on-Chip (NoC). As will become clear in the following, NoC does not constitute an explicit new alternative for intrachip communication but is rather a concept which presents a unification of on-chip communication solutions. In this section, we will first briefly review the history of microchip technology that has led to a call for NoC-based designs. With our minds on intrachip communication, This paper is a joint author effort, authors in alphabetical order. S. Mahadevan was funded by SoC-MOBINET (IST-2000-30094), Nokia and the Thomas B. Thrige Foundation. Authors��� address: Technical University of Denmark, Informatics and Mathematical Modelling, Richard Petersens Plads, Building 321, DK-2800 Lyngby, Denmark email:{tob,sm}@imm.dtu.dk. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or direct commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 1515 Broadway, New York, NY 10036 USA, fax: +1 (212) 869-0481, or permissions@acm.org. c 2006 ACM 0360-0300/06/0300-ART1 $5.00 http://doi.acm.org/10.1145/1132952.1132953 ACM Computing Surveys, Vol. 38, March 2006, Article 1.

2 T. Bjerregaard and S. Mahadevan Fig. 1. When a technology matures, it leads to a paradigm shift in system scope. Shown here is the chip scope in LSI, VLSI, and ULSI, the sequence of technologies leading to the enabling of SoC designs. we will then look at a number of key issues of large-scale chip design and finally show how the NoC concept provides a viable solution space to the problems presently faced by chip designers. 1.1. IntraSoC Communication The scaling of microchip technologies has lead to a doubling of available processing re- sources on a single chip every second year. Even though this is projected to slow down to a doubling every three years in the next few years for fixed chip sizes [ITRS 2003], the exponential trend is still in force. Though the evolution is continuous, the system level focus, or system scope, moves in steps. When a technology matures for a given implementation style, it leads to a paradigm shift. Examples of such shifts are mov- ing from room- to rack-level systems (LSI-1970s) and later from rack- to board-level systems (VLSI-1980s). Recent technological advances allowing multimillion transistor chips (currently well beyond 100M) have led to a similar paradigm shift from board- to chip-level systems (ULSI-1990s). The scope of a single chip has changed accordingly as illustrated in Figure 1. In LSI systems, a chip was a component of a system mod- ule (e.g., a bitslice in a bitslice processor), in VLSI systems, a chip was a system-level module (e.g., a processor or a memory), and in ULSI systems, a chip constitutes an entire system (hence the term System-on-Chip). SoC opens up the feasibility of a wide range of applications making use of massive parallel processing and tightly interde- pendent processes, some adhering to real-time requirements, bringing into focus new complex aspects of the underlying communication structure. Many of these aspects are addressed by NoC. There are multiple ways to approach an understanding of NoC. Readers well versed in macronetwork theory may approach the concept by adapting proven techniques from multicomputer networks. Much work done in this area during the 80s and 90s can readily be built upon. Layered communication abstraction models and decoupling of computation and communication are relevant issues. There are, however, a number of basic differences between on- and off-chip communication. These generally reflect the difference in the cost ratio between wiring and processing resources. Historically, computation has been expensive and communication cheap. With scaling microchip technologies, this changed. Computation is becoming ever cheaper, while communication encounters fundamental physical limitations such as time-of-flight of electrical signals, power use in driving long wires/cables, etc. In comparison with off- chip, on-chip communication is significantly cheaper. There is room for lots of wires on a chip. Thus the shift to single-chip systems has relaxed system communication problems. However on-chip wires do not scale in the same manner as transistors do, and, as we shall see in the following, the cost gap between computation and communication is ACM Computing Surveys, Vol. 38, March 2006.

A Survey of Research and Practices of Network-on-Chip 3 Fig. 2. Projected relative delay for local and global wires and for logic gates in technologies of the near future. [ITRS 2001]. widening. Meanwhile the differences between on- and off-chip wires make the direct scaling down of traditional multicomputer networks suboptimal for on-chip use. In this survey, we attempt to incorporate the whole range of design abstractions while relating to the current trends of intrachip communication. With the Giga Transistor Chip era close at hand, the solution space of intrachip communication is far from trivial. We have summarized a number of relevant key issues. Though not new, we find it worthwhile to go through them as the NoC concept presents a possible unification of solutions for these. In Section 3 and 4, we will look into the details of research being done in relation to these issues, and their relevance for NoC. ���Electrical wires. Even though on-chip wires are cheap in comparison with off-chip wires, on-chip communication is becoming still more costly in terms of both power and speed. As fabrication technologies scale down, wire resistance per-mm is in- creasing while wire capacitance does not change much the major part of the wire capacitance is due to edge capacitance [Ho et al. 2001]. For CMOS, the approximate point at which wire delays begin to dominate gate delays was the 0.25 ��m generation for aluminum, and 0.18 ��m for copper interconnects as first projected in SIA [1997]. Shrinking metal pitches, in order to maintain sufficient routing densities, is appro- priate at the local level where wire lengths also decrease with scaling. But global wire lengths do not decrease, and, as local processing cycle times decrease, the time spent on global communication relative to the time spent on local processing increases drastically. Thus in future deep submicron (DSM) designs, the interconnect effect will definitely dominate performance [Sylvester and Keutzer 2000]. Figure 2, taken from the International Technology Roadmap for Semiconductors [ITRS 2001], shows the ACM Computing Surveys, Vol. 38, March 2006.

4 T. Bjerregaard and S. Mahadevan projected relative delay for local wires, global wires, and logic gates in the near future. Another issue of pressing importance concerns signal integrity. In DSM technologies, the wire models are unreliable due to issues like fabrication uncertainties, crosstalk, noise sensitivity etc. These issues are especially applicable to long wires. Due to these effects of scaling, it has become necessary to differentiate between local and global communication, and, as transistors shrink, the gap is increasing. The need for global communication schemes supporting single-chip systems has emerged. ���System synchronization. As chip technologies scale and chip speeds increase, it is becoming harder to achieve global synchronization. The drawbacks of the predom- inant design style of digital integrated circuits, that is, strict global synchrony, are growing relative to the advantages. The clocktree needed to implement a globally synchronized clock is demanding increasing portions of the power and area budget, and, even so, the clock skew is claiming an ever larger relative part of the total cycle time available [Oklobdzija and Spars�� 2002 Oberg 2003]. This has triggered work on skew-tolerant circuit design [Nedovic et al. 2003], which deals with clockskew by relaxing the need for timing margins, and on the use of optical waveguides for on- chip clock distribution [Piguet et al. 2004], for the main purpose of minimizing power usage. Still, power hungry skew adjustment techniques such as phase locked loops (PLL) and delay locked loops (DLL), traditionally used for chip-to-chip synchroniza- tion, are finding their way into single-chip systems [Kurd et al. 2001 Xanthopoulos et al. 2001]. As a reaction to the inherent limitations of global synchrony, alternative concepts such as GALS (Globally Asynchronous Locally Synchronous systems) are being in- troduced. A GALS chip is made up of locally synchronous islands which communicate asynchronously [Chapiro 1984 Meincke et al. 1999 Muttersbach et al. 2000]. There are two main advantageous aspects of this method. One is the reducing of the syn- chronization problem to a number of smaller subproblems. The other relates to the integration of different IP (Intellectual Property) cores, easing the building of larger systems from individual blocks with different timing characteristics. ���Design productivity. The exploding amount of processing resources available in chip design together with a requirement for shortened design cycles have pushed the productivity burden on to chip designers. Between 1997 and 2002, the market demand reduced the typical design cycle by 50%. As a result of increased chip sizes, shrinking geometries, and the availability of more metal layers, the design complexity increased 50 times in the same period [OCPIP 2003a]. To keep up with these requirements, IP reuse is pertinent. A new paradigm for design methodology is needed which allows the design effort to scale linearly with system complexity. Abstraction at the register transfer level (RTL) was introduced with the ASIC design flow during the 90s, allowing synthesized standard cell design. This made it possible to design large chips within short design cycles, and synthesized RTL design is, at present, the defacto standard for making large chips quickly. But the availability of on-chip resources is outgrowing the productivity potential of even the ASIC design style. In order to utilize the exponential growth in number of transistors on each chip, even higher levels of abstraction must be applied. This can be done by introducing higher level communication abstractions, making a layered design methodology that enables a partitioning of the design effort into minimally interdependent subtasks. Support for this at the hardware level includes standard communication sockets which allow IP cores from different vendors to be plugged effortlessly together. This is particularly pertinent in complex multiprocessor system-on-chip (MPSoC) designs. Also, the development of design techniques to further increase the productivity of designers, is important. Electronic system level (ESL) design tools are necessary for supporting a design flow which make efficient use of such communication abstraction ACM Computing Surveys, Vol. 38, March 2006.

A Survey of Research and Practices of Network-on-Chip 5 Fig. 3. Examples of communication structures in Systems-on-Chip. a) traditional bus-based communication, b) dedicated point-to-point links, c) a chip area network. and design automation techniques and which make for seamless iterations across all abstraction levels. Pertaining to this, the complex, dynamic interdependency of data streams���arising when using a shared media for data traffic���threatens to foil the efforts of obtaining minimal interdependence between IP cores. Without special quality-of-service (QoS) support, the performance of data communication may become unwarrantly arbitrary [Goossens et al. 2005]. To ensure the effective exploitation of technology scaling, intelligent use of the available chip design resources is necessary at the physical as well as at the logical design level. The means to achieve this are through the development of effective and structured design methods and ESL tools. As shown, the major driving factors for the development of global communication schemes are the ever increasing density of on-chip resources and the drive to utilize these resources with a minimum of effort as well as the need to counteract the physical effects of DSM technologies. The trend is towards a subdivision of processing resources into manageable pieces. This helps reduce design cycle time since the entire chip design process can be divided into minimally interdependent subproblems. This also allows the use of modular verification methodologies, that is, verification at a low abstraction level of cores (and communication network) individually and at a high abstraction level of the system as a whole. Working at a high abstraction level allows a great degree of freedom from lower level issues. It also tends towards a differentiation of local and global communication. As intercore communication is becoming the performance bot- tleneck in many multicore applications, the shift in design focus is from a traditional processing-centric to a communication-centric one. One top-level aspect of this involves the possibility to save on global communication resources at the application level by in- troducing communication aware optimization algorithms in compilers [Guo et al. 2000]. System-level effects of technology scaling are further discussed in Catthoor et al. [2004]. A standardized global communication scheme, together with standard communica- tion sockets for IP cores, would make Lego brick-like plug-and-play design styles pos- sible, allowing good use of the available resources and fast product design cycles. 1.2. NoC in SoC Figure 3 shows some examples of basic communication structures in a sample SoC, for example, a mobile phone. Since the introduction of the SoC concept in the 90s, the solutions for SoC communication structures have generally been characterized by custom designed ad hoc mixes of buses and point-to-point links [Lahiri et al. 2001]. The ACM Computing Surveys, Vol. 38, March 2006.

6 T. Bjerregaard and S. Mahadevan Table I. Bus-versus-Network Arguments (Adapted from Guerrier and Greiner [2000]) Bus Pros & Cons Network Pros & Cons Every unit attached adds parasitic capacitance, therefore electrical performance degrades with growth. ��� + Only point-to-point one-way wires are used, for all network sizes, thus local performance is not degraded when scaling. Bus timing is difficult in a deep submicron process. ��� + Network wires can be pipelined because links are point-to-point. Bus arbitration can become a bottleneck. The arbitration delay grows with the number of masters. ��� + Routing decisions are distributed, if the network protocol is made non-central. The bus arbiter is instance-specific. ��� + The same router may be reinstantiated, for all network sizes. Bus testability is problematic and slow. ��� + Locally placed dedicated BIST is fast and offers good test coverage. Bandwidth is limited and shared by all units attached. ��� + Aggregated bandwidth scales with the network size. Bus latency is wire-speed once arbiter has granted control. + ��� Internal network contention may cause a latency. Any bus is almost directly compatible with most available IPs, including software running on CPUs. + ��� Bus-oriented IPs need smart wrappers. Software needs clean synchronization in multiprocessor systems. The concepts are simple and well understood. + ��� System designers need reeducation for new concepts. bus builds on well understood concepts and is easy to model. In a highly interconnected multicore system, however, it can quickly become a communication bottleneck. As more units are added to it, the power usage per communication event grows as well due to more attached units leading to higher capacitive load. For multimaster busses, the problem of arbitration is also not trivial. Table I summarizes the pros and cons of buses and networks. A crossbar overcomes some of the limitations of the buses. However, it is not ultimately scalable and, as such, it is an intermediate solution. Dedicated point-to- point links are optimal in terms of bandwidth availability, latency, and power usage as they are designed especially for this given purpose. Also, they are simple to design and verify and easy to model. But the number of links needed increases exponentially as the number of cores increases. Thus an area and possibly a routing problem develops. From the point of view of design-effort, one may argue that, in small systems of less than 20 cores, an ad hoc communication structure is viable. But, as the systems grow and the design cycle time requirements decrease, the need for more generalized solutions becomes pressing. For maximum flexibility and scalability, it is generally accepted that a move towards a shared, segmented global communication structure is needed. This notion translates into a data-routing network consisting of communication links and routing nodes that are implemented on the chip. In contrast to traditional SoC communication methods outlined previously, such a distributed communication media scales well with chip size and complexity. Additional advantages include increased aggregated performance by exploiting parallel operation. From a technological perspective, a similar solution is reached: in DSM chips, long wires must be segmented in order to avoid signal degradation, and busses are imple- mented as multiplexed structures in order to reduce power and increase responsiveness. Hierarchical bus structures are also common as a means to adhere to the given commu- nication requirements. The next natural step is to increase throughput by pipelining ACM Computing Surveys, Vol. 38, March 2006.

A Survey of Research and Practices of Network-on-Chip 7 these structures. Wires become pipelines and bus-bridges become routing nodes. Expanding on a structure using these elements, one gets a simple network. A common concept for segmented SoC communication structures is based on net- works. This is what is known as Network-on-Chip (NoC) [Agarwal 1999 Guerrier and Greiner 2000 Dally and Towles 2001 Benini and Micheli 2002 Jantsch and Tenhunen 2003]. As presented previously, the distinction between different communication so- lutions is fading. NoC is seen to be a unifying concept rather than an explicit new alternative. In the research community, there are two widely held perceptions of NoC: (i) that NoC is a subset of SoC, and (ii) that NoC is an extension of SoC. In the first view, NoC is defined strictly as the data-forwarding communication fabric, that is, the network and methods used in accessing the network. In the second view NoC is defined more broadly to also encompass issues dealing with the application, system architec- ture, and its impact on communication or vice versa. 1.3. Outline The purpose of this survey is to clarify the NoC concept and to map the scientific efforts made into the area of NoC research. We will identify general trends and explain a range of issues which are important for state-of-the-art global chip-level communication. In doing so, we primarily take the first view of NoC, that is, that it is a subset of SoC, to focus and structure the diverse discussion. From our perspective, the view of NoC as an extension of SoC muddles the discussion with topics common to any large-scale IC de- sign effort such as partitioning and mapping application, hardware/software codesign, compiler choice, etc. The rest of the survey is organized as follows. In Section 2, we will discuss the ba- sics of NoC. We will give a simple NoC example, address some relevant system-level architectural issues, and relate the basic building blocks of NoC to abstract network layers and research areas. In Section 3, we will go into more details of existing NoC re- search. This section is partitioned according to the research areas defined in Section 2. In Section 4, we discuss high abstraction-level issues such as design space exploration and modeling. These are issues often applicable to NoC only in the view of it as an extension of SoC, but we treat specifically issues of relevance to NoC-based designs and not to large scale IC designs in general. In Section 5, performance analysis is ad- dressed. Section 6 presents a set of case studies describing a number of specific NoC implementations, and Section 7 summarizes the survey. 2. NOC BASICS In this section, the basics of NoC are uncovered. First a component-based view will be presented, introducing the basic building blocks of a typical NoC. Then we will look at system-level architectural issues relevant to NoC-based SoC designs. After this, a layered abstraction-based view will be presented, looking at network abstraction models, in particular, OSI and the adaption of such for NoC. Using the foundations established in this section, we will go into further details of specific NoC research in Section 3. 2.1. A Simple NoC Example Figure 4 shows a sample NoC structured as a 4-by-4 grid which provides global chip- level communication. Instead of busses and dedicated point-to-point links, a more gen- eral scheme is adapted, employing a grid of routing nodes spread out across the chip, connected by communication links. For now, we will adapt a simplified perspective in ACM Computing Surveys, Vol. 38, March 2006.

8 T. Bjerregaard and S. Mahadevan Fig. 4. Topological illustration of a 4-by-4 grid structured NoC, in- dicating the fundamental components. which the NoC contains the following fundamental components. ���Network adapters implement the interface by which cores (IP blocks) connect to the NoC. Their function is to decouple computation (the cores) from communication (the network). ���Routing nodes route the data according to chosen protocols. They implement the routing strategy. ���Links connect the nodes, providing the raw bandwidth. They may consist of one or more logical or physical channels. Figure 4 covers only the topological aspects of the NoC. The NoC in the figure could thus employ packet or circuit switching or something entirely different and be imple- mented using asynchronous, synchronous, or other logic. In Section 3, we will go into details of specific issues with an impact on the network performance. 2.2. Architectural Issues The diversity of communication in the network is affected by architectural issues such as system composition and clustering. These are general properties of SoC but, since they have direct influence on the design of the system-level communication infrastruc- ture, we find it worthwhile to go through them here. Figure 5 illustrates how system composition can be categorized along the axes of homogenity and granularity of system cores. The figure also clarifies a basic difference between NoC and networks for more traditional parallel computers the latter have gen- erally been homogeneous and coarse grained, whereas NoC-based systems implement a much higher degree of variety in composition and in traffic diversity. Clustering deals with the localization of portions of the system. Such localization may be logical or physical. Logical clustering can be a valuable programming tool. It can be supported by the implementation of hardware primitives in the network, for example, flexible addressing schemes or virtual connections. Physical clustering, based on preexisting knowledge of traffic patterns in the system, can be used to minimize global communication, thereby minimizing the total cost of communicating, power and performancewise. ACM Computing Surveys, Vol. 38, March 2006.

A Survey of Research and Practices of Network-on-Chip 9 Fig. 5. System composition categorized along the axes of homogenity and granularity of system com- ponents. Generally speaking, reconfigurability deals with the ability to allocate available re- sources for specific purposes. In relation to NoC-based systems, reconfigurability con- cerns how the NoC, a flexible communication structure, can be used to make the system reconfigurable from an application point of view. A configuration can be established for example, by programming connections into the NoC. This resembles the reconfigurabil- ity of an FPGA, though NoC-based reconfigurability is most often of coarser granularity. In NoC, the reconfigurable resources are the routing nodes and links rather than wires. Much research work has been done on architecturally-oriented projects in relation to NoC-based systems. The main issue in architectural decisions is the balancing of flexibility, performance, and hardware costs of the system as a whole. As the underlying technology advances, the trade-off spectrum is continually shifted, and the viability of the NoC concept has opened up to a communication-centric solution space which is what current system-level research explores. At one corner of the architecural space outlined in Figure 5, is the Pleiades ar- chitecture [Zhang et al. 2000] and its instantiation, the Maia processor. A micropro- cessor is combined with a relatively fine-grained heterogeneous collection of ALUs, memories, FPGAs, etc. An interconnection network allows arbitrary communication between modules of the system. The network is hierarchical and employs clustering in order to provide the required communication flexibility while maintaining good energy-efficiency. At the opposite corner are a number of works, implementing homogeneous coarse- grained multiprocessors. In Smart Memories [Mai et al. 2000], a hierarchical network is used with physical clustering of four processors. The flexibility of the local cluster network is used as a means for reconfigurability, and the effectiveness of the plat- form is demonstrated by mimicking two machines on far ends of the architectural spectrum, the Imagine streaming processor and Hydra multiprocessor, with modest performance degradation. The global NoC is not described, however. In the RAW ar- chitecture [Taylor et al. 2002], on the other hand, the NoC which interconnects the processor tiles is described in detail. It consists of a static network, in which the com- munication is preprogrammed cycle-by-cycle, and a dynamic network. The reason for implementing two physically separate networks is to accommodate different types of traffic in general purpose systems (see Section 4.3 concerning traffic characterization). The Eclipse [Forsell 2002] is another similarly distributed multiprocessor architecture ACM Computing Surveys, Vol. 38, March 2006.

10 T. Bjerregaard and S. Mahadevan Fig. 6. The flow of data from source to sink through the NoC components with an indication of the types of datagrams and research area. in which the interconnection network plays an important role. Here, the NoC is a key element in supporting a sofisticated parallel programming model. 2.3. Network Abstraction The term NoC is used in research today in a very broad sense ranging from gate- level physical implementation, across system layout aspects and applications, to de- sign methodologies and tools. A major reason for the widespread adaptation of network terminology lies in the readily available and widely accepted abstraction models for networked communication. The OSI model of layered network communication can eas- ily be adapted for NoC usage as done in Benini and Micheli [2001] and Arteris [2005]. In the following, we will look at network abstraction, and make some definitions to be used later in the survey. To better understand the approaches of different groups involved in NoC, we have partitioned the spectrum of NoC research into four areas: 1) system, 2) network adapter, 3) network and 4) link research. Figure 6 shows the flow of data through the network, indicating the relation between these research areas, the fundamental components of NoC, and the OSI layers. Also indicated is the basic datagram terminology. The system encompasses applications (processes) and architecture (cores and net- work). At this level, most of the network implementation details may still be hidden. Much research done at this level is applicable to large scale SoC design in general. The network adapter (NA) decouples the cores from the network. It handles the end- to-end flow control, encapsulating the messages or transactions generated by the cores for the routing strategy of the Network. These are broken into packets which contain information about their destination, or connection-oriented streams which do not, but have had a path setup prior to transmission. The NA is the first level which is network aware. The network consists of the routing nodes, links, etc, defining the topology and implementing the protocol and the node-to-node flow control. The lowest level is the link level. At this level, the basic datagram are flits (flow control units), node level atomic units from which packets and streams are made up. Some researchers operate with yet another subdivision, namely phits (physical units), which are the minimum size datagram that can be transmitted in one link transaction. Most commonly flits and phits are equivalent, though in a network employing highly serialized links, each flit could be made up of a sequence of phits. Link-level research deals mostly with ACM Computing Surveys, Vol. 38, March 2006.

A Survey of Research and Practices of Network-on-Chip 11 Fig. 7. NoC research area classification. This classification, which also forms the structure of Section 3, is meant as a guideline to evaluate NoC research and not as a technical categorization. encoding and synchronization issues. The presented datagram terminology seems to be generally accepted, though no standard exists. In a NoC, the layers are generally more closely bound than in a macronetwork. Issues arising often have a more physically-related flavor even at the higher abstraction levels. OSI specifies a protocol stack for multicomputer networks. Its aim is to shield higher levels of the network from issues of lower levels in order to allow communication be- tween independently developed systems, for example, of different manufacturers, and to allow ongoing expansion of systems. In comparison with macronetworks, NoC bene- fits from the system composition being completely static. The network can be designed based on knowledge of the cores to be connected and also possibly on knowledge of the characteristics of the traffic to be handled, as demonstrated in for example, Bolotin et al. [2004] and Goossens et al. [2005]. Awareness of lower levels can be beneficial as it can lead to higher performance. The OSI layers, which are defined mainly on the basis of pure abstraction of communication protocols, thus cannot be directly translated into the research areas defined here. With this in mind, the relation established in Figure 6 is to be taken as a conceptual guideline. 3. NOC RESEARCH In this section, we provide a review of the approaches of various research groups. Figure 7 illustrates a simplified classification of this research. The text is structured based on the layers defined in Section 2.3. Since we consider NoC as a subset of SoC, system-level research is dealt with separately in Section 4. 3.1. Network Adapter The purpose of the network adapter (NA) is to interface the core to the network and make communication services transparently available with a minimum of effort from ACM Computing Surveys, Vol. 38, March 2006.

12 T. Bjerregaard and S. Mahadevan Fig. 8. The network adapter (NA) implements two interfaces, the core interface (CI) and the network interface (NI). the core. At this point, the boundary between computation and communication is specified. As illustrated in Figure 8, the NA component implements a core interface (CI) at the core side and a network interface (NI) at the network side. The function of the NA is to provide high-level communication services to the core by utilizing primitive services provided by the network hardware. Thus the NA decouples the core from the network, implementing the network end-to-end flow control, facilitating a layered system design approach. The level of decoupling may vary. A high level of decoupling allows for easy reuse of cores. This makes possible a utilization of the exploding resources available to chip designers, and greater design productivity is achieved. On the other hand, a lower level of decoupling (a more network aware core) has the potential to make more optimal use of the network resources. In this section, we first address the use of standard sockets. We then discuss the ab- stract functionality of the NA. Finally, we talk about some actual NA implementations which also address issues related to timing and synchronization. 3.1.1. Sockets. The CI of the NA may be implemented to adhere to a SoC socket standard. The purpose of a socket is to orthogonalize computation and communication. Ideally a socket should be completely NoC implementation agnostic. This will facilitate the greatest degree of reusability because the core adheres to the specification of the socket alone, independently of the underlying network hardware. One commonly used socket is the Open Core Protocol (OCP) [OCPIP 2003b Haverinen et al. 2002]. The OCP specification defines a flexible family of memory-mapped, core-centric protocols for use as a native core interface in on-chip systems. The three primary properties envisioned in OCP include (i) architecture independent design reuse, (ii) feature-specific socket im- plementation, and (iii) simplification of system verification and testing. OCP addresses not only dataflow signaling, but also uses related to errors, interrupts, flags and soft- ware flow control, control and status, and test. Another proposed standard is the Virtual Component Interface (VCI) [VSI Alliance 2000] used in the SPIN [Guerrier and Greiner 2000] and Proteo [Siguenza-Tortosa et al. 2004] NoCs. In Radulescu et al. [2004], sup- port for the Advanced eXtensible Interface (AXI) [ARM 2004] and Device Transaction Level (DTL) [Philips Semiconductors 2002] protocols was also implemented in an NA design. ACM Computing Surveys, Vol. 38, March 2006.

A Survey of Research and Practices of Network-on-Chip 13 3.1.2. NA Services. Basically, the NA provides encapsulation of the traffic for the un- derlying communication media and management of services provided by the network. Encapsulation involves handling of end-to-end flow control in the network. This may include global addressing and routing tasks, reorder buffering and data acknowledge- ment, buffer management to prevent network congestion, for example, based on credit, packet creation in a packet-switched network, etc. Cores will contend for network resources. These may be provided in terms of ser- vice quantification, for example, bandwidth and/or latency guarantees (see also Sec- tions 3.2.4 and 5). Service management concerns setting up circuits in a circuit-switched network, bookkeeping tasks such as keeping track of connections, and matching re- sponses to requests. Another task of the NA could be to negotiate the service needs between the core and the network. 3.1.3. NA Implementations. A clear understanding of the role of the NA is essential to successful NoC design. Muttersbach et al. [2000] address synchronization issues, proposing a design of an asynchronous wrapper for use in a practical GALS design. Here the synchronous modules are equipped with asynchronous wrappers which adapt their interfaces to the self-timed environment. The packetization occurs within the synchronous module. The wrappers are assembled from a concise library of predesigned technology-independent elements and provide high speed data transfer. Another mixed asynchronous/synchronous NA architecture is proposed in Bjerregaard et al. [2005]. Here, a synchronous OCP interface connects to an asynchronous, message-passing NoC. Packetization is performed in the synchronous domain, while sequencing of flits is done in the asynchronous domain. This makes the sequencing independent of the speed of the OCP interface, while still taking advantage of synthesized synchronous design for maintaining a flexible packet format. Thus the NA leverages the advantages particular to either circuit design style. In Radulescu et al. [2004], a complete NA design for the AETHEREAL NoC is presented which also offers a shared-memory abstraction to the cores. It provides compatibility to existing on-chip protocols such as AXI, DTL, and OCP and allows easy extension to other future protocols as well. However, the cost of using standard sockets is not trivial. As demonstrated in the HERMES NoC [Ost et al. 2005], the introduction of OCP makes the transactions up to 50% slower compared to the native core interface. An interesting design trade-off issue is the partitioning of the NA functions between software (possibly in the core) and hardware (most often in the NA). In Bhojwani and Mahapatra [2003], a comparison of software and hardware implementations of the packetization task was undertaken, the software taking 47 cycles to complete, while the hardware version took only 2 cycles. In Radulescu et al. [2004], a hardware implementation of the entire NA introduces a latency overhead of between 4 and 10 cycles, pipelined to maximize throughput. The NA in Bjerregaard et al. [2005] takes advantage of the low forward latency of clockless circuit techniques, introducing an end-to-end latency overhead of only 3 to 5 cycles for writes and 6 to 8 cycles for reads which include data return. 3.2. Network Level The job of the network is to deliver messages from their source to their designated destination. This is done by providing the hardware support for basic communication primitives. A well-built network, as noted by Dally and Towles [2001], should appear as a logical wire to its clients. An on-chip network is defined mainly by its topology and the protocol implemented by it. Topology concerns the layout and connectivity of the nodes and links on the chip. Protocol dictates how these nodes and links are used. ACM Computing Surveys, Vol. 38, March 2006.

14 T. Bjerregaard and S. Mahadevan Fig. 9. Regular forms of topologies scale predictably with regard to area and power. Examples are (a) 4-ary 2-cube mesh, (b) 4-ary 2-cube torus and (c) binary (2-ary) tree. Fig. 10. Irregular forms of topologies are derived by altering the connectivity of a regular structure such as shown in (a) where certain links from a mesh have been removed or by mixing different topologies such as in (b) where a ring coexists with a mesh. 3.2.1. Topology. One simple way to distinguish different regular topologies is in terms of k-ary n-cube (grid-type), where k is the degree of each dimension and n is the number of dimensions (Figure 9), first described by Dally [1990] for multicomputer networks. The k-ary tree and the k-ary n-dimensional fat tree are two alternate regular forms of networks explored for NoC. The network area and power consumption scales pre- dictably for increasing size of regular forms of topology. Most NoCs implement regular forms of network topology that can be laid out on a chip surface (a 2-dimensional plane) for example, k-ary 2-cube, commonly known as grid-based topologies. The Octagon NoC demonstrated in Karim et al. [2001, 2002] is an example of a novel regular NoC topol- ogy. Its basic configuration is a ring of 8 nodes connected by 12 bidirectional links which provides two-hop communication between any pair of nodes in the ring and a simple, shortest-path routing algorithm. Such rings are then connected edge-to-edge to form a larger, scalable network. For more complex structures such as trees, finding the optimal layout is a challenge on its own right. Besides the form, the nature of links adds an additional aspect to the topology. In k-ary 2-cube networks, popular NoC topologies based on the nature of link are the mesh which uses bidirectional links and torus which uses unidirectional links. For a torus, a folding can be employed to reduce long wires. In the NOSTRUM NoC presented in Millberg et al. [2004], a folded torus is discarded in favor of a mesh with the argument that it has longer delays between routing nodes. Figure 9 shows examples of regular forms of topology. Generally, mesh topology makes better use of links (utilization), while tree-based topologies are useful for exploiting locality of traffic. Irregular forms of topologies are derived by mixing different forms in a hierarchical, hybrid, or asymmetric fashion as seen in Figure 10. Irregular forms of topologies scale ACM Computing Surveys, Vol. 38, March 2006.

A Survey of Research and Practices of Network-on-Chip 15 Fig. 11. Two layout concepts. The thin switch is distributed around the cores, and wires are routed across it. The square switch is placed on the crossings in dedicated channels between the cores. nonlinearly with regards to area and power. These are usually based on the concept of clustering. A small private/local network often implemented as a bus [Mai et al. 2000 Wielage and Goossens 2002] for local communication with k-ary 2-cube global communication is a favored solution. In Pande et al. [2005], the impact of clustering on five NoC topologies is presented. It shows 20% to 40% reduction in bit-energy for the same amount of throughput due to traffic localization. With regard to the presence of a local traffic source or sink connected to the node, direct networks are those that have at least one core attached to each node indirect networks, on the other hand, have a subset of nodes not connected to any core, perform- ing only network operations as is generally seen in tree-based topology where cores are connected at the leaf nodes. The examples of indirect tree-based networks are fat-tree in SPIN [Guerrier and Greiner 2000] and butterfly in Pande et al. [2003]. The fat-tree used in SPIN is proven in Leiserson [1985] to be most hardware efficient compared to any other network. For alternate classifications of topology, the reader is referred to Aggarwal and Franklin [2002], Jantsch [2003], and Culler et al. [1998]. Culler et al. [1998] combine protocol and geometry to bring out a new type of classification which is defined as topology. With regards to the routing nodes, a layout trade-off is the thin switch vs square switch presented by Kumar et al. [2002]. Figure 11 illustrates the difference between these two layout concepts. A thin switch is distributed around the cores, and wires are routed across them. A square switch is placed on the crossings of dedicated wiring channels between the cores. It was found that the square switch is better for perfor- mance and bandwidth, while the thin switch requires relatively low area. The area overhead required to implement a NoC is in any case expected to be modest. The processing logic of the router for a packet switched network is estimated to be ap- proximately between 2.0% [Pande et al. 2003] to 6.6% [Dally and Towles 2001] of the total chip area. In addition to this, the wiring uses a portion of the upper two wiring layers. 3.2.2. Protocol. The protocol concerns the strategy of moving data through the NoC. We define switching as the mere transport of data, while routing is the intelligence behind it, that is, it determines the path of the data transport. This is in accordance with Culler et al. [1998]. In the following, these and other aspects of protocol commonly ACM Computing Surveys, Vol. 38, March 2006.