High Performance Computations with Sparse and Stencil Operators

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Sidney R. Santana is now following this group

26th March

Tareq Malas added a document to this group

Introducing a Performance Model for Bandwidth-Limited Loop Kernels

4th February

Wim Vanroose added a document to this group

Improving the arithmetic intensity of multigrid with the help of polynomial smoothers

30th November, 2011

Wim Vanroose likes this.

Tareq Malas added a document to this group

Languages and Compilers for Parallel Computing

12th October, 2011

Tareq Malas added documents to this group

P ATUS : A Code Generation and Auto-Tuning Framework For Parallel Stencil Computations

PATUS: A Code Generation and Auto-Tuning Framework For Parallel Stencil Computations

Automatic code generation and tuning for stencil kernels on modern shared memory architectures

PATUS: A Code Generation and Autotuning Framework for Parallel Iterative Stencil Computations on Modern Microarchitectures

Parallel data-locality aware stencil computations on modern micro-architectures

And 3 more

11th October, 2011

Tareq Malas added a document to this group

Postpass Code Optimization of Pipeline Constraints

14th September, 2011

Tareq Malas added documents to this group

Retargetable Code Optimisation by Integer Linear Programming

Optimal Superblock Instruction Scheduling for

Ant colony optimizations for resource-and timing-constrained operation scheduling

Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques

Optimal integrated vliw code generation with integer linear programming

And 7 more

6th September, 2011

Jed Brown has joined this group

29th June, 2011

Tareq Malas added a document to this group

The algorithm design manual

22nd June, 2011

Aron Ahmadia added documents to this group

Compiler Construction

Mechanical Derivation of Fused Multiply–Add Algorithms for Linear Transforms

Optimal instruction scheduling using integer programming

Using integer linear programming for instruction scheduling and register allocation in multi-issue processors• 1

And 1 more

21st June, 2011

Tareq Malas added a document to this group

Memory Bandwidth and Machine Balance in Current High Performance Computers

15th June, 2011

Aron Ahmadia added a document to this group

3 . 5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs

5th May, 2011

Tareq Malas added a document to this group

Combined iterative and model-driven optimization in an automatic parallelization framework

2nd May, 2011

Tareq Malas added documents to this group

Fortran at ten gigaflops: The Connection Machine convolution compiler

Tuned and wildly asynchronous stencil kernels for hybrid CPU/GPU systems

Strider: Runtime support for optimizing strided data accesses on multi-cores with explicitly managed memories

1st May, 2011

Tareq Malas added documents to this group

Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures

Auto-vectorization of interleaved data for SIMD

Vectorization for SIMD architectures with alignment constraints

30th April, 2011

Tareq Malas added documents to this group

No Title

Beyond homogeneous decomposition: scaling long-range forces on Massively Parallel Systems

No Title

Indexing genomic sequences on the IBM Blue Gene

The cat is out of the bag: cortical simulations with 109 neurons, 1013 synapses

And 2 more

18th April, 2011

Aron Ahmadia added documents to this group

The NAS parallel benchmarks

Exaflop/s: The why and the how

The NAS parallel benchmarks

The green500 list: Encouraging sustainable supercomputing

15th April, 2011

Tareq Malas added documents to this group

Estimating interlock and improving balance for pipelined architectures• 1

Improving the ratio of memory operations to floating-point operations in loops

Loop quantization: An analysis and algorithm

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

A multigrid tutorial

And 3 more

14th April, 2011

Tareq Malas added a document to this group

Intel’s Array Building Blocks: A Retargetable, Dynamic Compiler and Embedded Language

9th April, 2011

Tareq Malas added documents to this group

Optimizations for quadrature representations of finite element tensors through automated code generation

Combining loop transformations considering caches and scheduling

8th April, 2011

Owned by Aron Ahmadia

Researcher (at an Academic Institution)

Mathematics

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High Performance Computations with Sparse and Stencil Operators

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