Dean Truong, M.S., B.S.
Research Assistant at the VLSI Computation Laboratory, University of California, DavisDavis, California, United States
Research field: Electrical and Electronic Engineering - Circuits and Systems
Many-core DSP HW/SW implementation. Energy-efficient computation through DVFS. Modeling many-core architectures to analyze real-time throughput and latency of deployed large-scale applications. Ultrasound signal and image processing on many-core chips.
Publications
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Journal Article (5)
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Tinoosh Mohsenin, Dean N Truong, Bevan M Baas (2010) A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders, 1048-1061. In IEEE Transactions on Circuits and Systems I: Regular Papers 57 (5).
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Anh Thien Tran, Dean Nguyen Truong, Bevan Baas (2010) A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms, 897-910. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29 (6).
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Dean N Truong, Wayne H Cheng, Tinoosh Mohsenin et al. (2009) A 167-Processor Computational Platform in 65 nm CMOS, 1130-1144. In IEEE Journal of Solid-State Circuits 44 (4).
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Zhiyi Yu, Michael J Meeuwsen, Ryan W Apperson et al. (2008) AsAP: An Asynchronous Array of Simple Processors, 695-705. In IEEE Journal of Solid-State Circuits 43 (3).
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Bevan Baas, Zhiyi Yu, Michael Meeuwsen et al. (2007) AsAP: A Fine-Grained Many-Core Platform for DSP Applications, 34-45. In IEEE Micro 27 (2).
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Conference Proceedings (11)
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Dean N Truong, Bevan M Baas (2010) Circuit modeling for practical many-core architecture design exploration, 627. In Proceedings of the 47th Design Automation Conference on - DAC '10.
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Dean N Truong, Bevan M Baas (2010) Massively parallel processor array for mid-/back-end ultrasound signal processing, 274-277. In 2010 Biomedical Circuits and Systems Conference (BioCAS).
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Anh T Tran, Dean N Truong, Bevan M Baas (2009) A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network, 214-223. In 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
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Anh T Tran, Dean N Truong, Bevan M Baas (2009) A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors, 996-999. In 2009 IEEE International Symposium on Circuits and Systems.
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T Mohsenin, D Truong, B Baas (2009) An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes, 1-5. In 2009 IEEE International Conference on Communications.
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Tinoosh Mohsenin, Dean Truong, Bevan Baas (2009) Multi-Split-Row Threshold decoding implementations for LDPC codes, 2449-2452. In 2009 IEEE International Symposium on Circuits and Systems.
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Anthony T Jacobson, Dean N Truong, Bevan M Baas (2009) The design of a reconfigurable continuous-flow mixed-radix FFT processor, 1133-1136. In 2009 IEEE International Symposium on Circuits and Systems.
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Dean Truong, Wayne Cheng, Tinoosh Mohsenin et al. (2008) A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling, 22-23. In 2008 IEEE Symposium on VLSI Circuits.
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Dean Truong, Wayne Cheng, Tinoosh Mohsenin et al. (2008) A 167-processor Computational Array for Highly-Efficient DSP and Embedded Application Processing. In IEEE HotChips Symposium on High-Performance Chips (HotChips 2008).
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Anh T Tran, Dean N Truong, Bevan M Baas (2008) A complete real-time 802.11a baseband receiver implemented on an array of programmable processors, 165-170. In 2008 42nd Asilomar Conference on Signals, Systems and Computers.
- See all
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Awards and Grants
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Dec 2010Graduate Student Travel Award View website
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Mar 2009Block Grant fellowship View website
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Mar 2006UC Microelectronics Innovation and Computer Research Opportunities (MICRO) fellowship View website
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Sep 2005Graduate Assistance in Areas of National Need (GAANN) fellowship View website
Biographical Information
Authored and co-authored 16 papers in top circuits journals and conferences, including the IEEE Journal of Solid State Circuits, VLSI Symposium on Technology and Circuits, IEEE Transactions on Circuits and Systems, HotChips Symposia on High Performance Processors, and ACM/IEEE Design Automation Conference.
Currently pursuing ideas in modeling real-time embedded systems to meet throughput, latency and energy requirements, and deploying circuits, architectures, and software to meet these targets. Looking into ultrasound signal and image processing application mapping on many-core processors.
Goals: Start gaining experience by working in industry or continue my academic career as a postdoc in Biomedical Engineering.
Specialties:
Digital Integrated Circuit Design,
Digital Systems and Computer Architecture,
RTL Engineer,
Back-end Design and Verification,
Lab Instrumentation & Chip Testing,
Embedded Software Development,
Biomedical Imaging on Massively Parallel Processor Arrays
===========================
My publication statistics thus far:
Papers: 15
Cites/paper: 5.20
h-index: 5
AWCR: 16.17
Citations: 78
Cites/author: 17.31
g-index: 8
AW-index: 4.02
Years: 4
Papers/author: 4.23
hc-index: 7
AWCRpA: 4.28
Cites/year: 19.50
Authors/paper: 4.07
hI-index: 0.96
e-index: 5.39
hI,norm: 2
hm-index: 2.19
Hirsch a=3.12, m=1.25
Contemporary ac=1.33
Cites/paper 5.20/4.0/5 (mean/median/mode)
Authors/paper 4.07/3.0/3 (mean/median/mode)
1 paper(s) with 2 author(s)
8 paper(s) with 3 author(s)
3 paper(s) with 5 author(s)
1 paper(s) with 6 author(s)
2 paper(s) with 7 author(s)
===========================
Currently pursuing ideas in modeling real-time embedded systems to meet throughput, latency and energy requirements, and deploying circuits, architectures, and software to meet these targets. Looking into ultrasound signal and image processing application mapping on many-core processors.
Goals: Start gaining experience by working in industry or continue my academic career as a postdoc in Biomedical Engineering.
Specialties:
Digital Integrated Circuit Design,
Digital Systems and Computer Architecture,
RTL Engineer,
Back-end Design and Verification,
Lab Instrumentation & Chip Testing,
Embedded Software Development,
Biomedical Imaging on Massively Parallel Processor Arrays
===========================
My publication statistics thus far:
Papers: 15
Cites/paper: 5.20
h-index: 5
AWCR: 16.17
Citations: 78
Cites/author: 17.31
g-index: 8
AW-index: 4.02
Years: 4
Papers/author: 4.23
hc-index: 7
AWCRpA: 4.28
Cites/year: 19.50
Authors/paper: 4.07
hI-index: 0.96
e-index: 5.39
hI,norm: 2
hm-index: 2.19
Hirsch a=3.12, m=1.25
Contemporary ac=1.33
Cites/paper 5.20/4.0/5 (mean/median/mode)
Authors/paper 4.07/3.0/3 (mean/median/mode)
1 paper(s) with 2 author(s)
8 paper(s) with 3 author(s)
3 paper(s) with 5 author(s)
1 paper(s) with 6 author(s)
2 paper(s) with 7 author(s)
===========================
CV
Professional Experience
2006 - Present
Research Assistant at the VLSI Computation Laboratory at University of California, Davis
Davis, California, United States
Davis, California, United States
Oct 2009 - Sep 2010
President of the Electrical and Computer Engineering Graduate Student Association at University of California, Davis
Davis, California, United States
Davis, California, United States
Jan 2009 - May 2010
Laboratory Manager at the VLSI Computation Laboratory at University of California, Davis
Davis, California, United States
Davis, California, United States
Education
2010 - Present
University of California, Davis
in Davis, California, United States
Ph.D. Candidate in Electrical and Computer Engineering
Ph.D. Candidate in Electrical and Computer Engineering
Sep 2005 - May 2010
University of California, Davis
in Davis, California, United States
M.S. in Electrical and Computer Engineering
M.S. in Electrical and Computer Engineering
Sep 2001 - Jun 2005
University of California, Davis
in Davis, California, United States
B.S. in Electrical and Computer Engineering
B.S. in Electrical and Computer Engineering
Contact Information
| Webpage: | http://www.ece.ucdavis.edu/vcl/ |
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