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Papers in Systems and Control Theory

Systems and Control Theory papers in Computer and Information Science, A

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Papers 1 - 20 of 5,666 in Systems and Control Theory, A
  1. The aims of this randomized, single-blind crossover trial were to investigate the effect of adding a simulated bowling video game via the Nintendo Wii() gaming system to the standard exercise regimen of cognitively intact residents of long-term care…
  2. This paper presents a 10-bit 40-MS/s pipelined ADC in a 0.13-&x03BC;m CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling,…
  3. A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are…
  4. We propose a novel control method for lower- limb assist that produces a virtual modification of the mechanical impedance of the human limbs. This effect is accomplished through the use of an exoskeleton that displays active impedance. The proposed…
  5. This brief presents an efficient and configurable multiple-input-multiple-output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 &x00D7; 2/3 &x00D7; 3/4 &x00D7; 4 MIMO and quadratic…
  6. This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce…
  7. This paper presents a 10.0&x223C;11.5 Gb/s full-rate phase and frequency detector integrated with the clock recovery circuit (CRC) for application in optical receivers. A rotational phase and frequency detector (RPFD) without external reference…
  8. A 10-bit 300 MSample/s pipelined analog to digital converter (ADC) using time-interleaved successive approximation register (SAR) ADC in the first stage is presented. By replacing the front-end pipelined stages with energy-efficient SAR-ADC, power…
  9. A 10-bit 60-MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit is employed to enhance the dynamic performance of…
  10. We aim at developing ultralight autonomous microflyers capable of navigating within houses or small built environments. Our latest prototype is a fixed-wing aircraft weighing a mere 10 g, flying below 2 m/s and carrying the necessary electronics for…
  11. A CMOS operational amplifier that has a common-mode rejection ratio (CMRR), a power-supply rejection ratio (PSRR), and gain above 100 dB for each of these parameters is described. This is achieved by combining a high output-impedance tail current…
  12. A novel bulk mode MEMS resonator is presented where mechanical motion is detected using the piezoresistive properties of Si. The piezoresistive readout allows for a high transduction efficiency. The transconductance gm obtained in this manner can be…
  13. This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential…
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