Papers in Circuits and Systems

Circuits and Systems papers in Electrical and Electronic Engineering, A

Papers 1 - 20 of 7,438 in Circuits and Systems, A

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1. Общественная Aрхеология Англии

   M Machizawa in Society (2010)

   We tested the hypothesis that single nucleotide polymorphisms (SNPs) within genes of the NF-κB pathway are associated with altered clinical outcome of septic shock patients. We genotyped 59 SNPs in the NF-κB pathway in a discovery cohort of septic…

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2. A 0.013mm2, 5uW, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

   Rikky Muller, Simone Gambini, Jan M Rabaey in IEEE Journal of Solid State Circuits (2012)

   We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a…

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3. A 0.01%THD, 70dB PSRR Single Ended Class D using variable hysteresis control for headphone amplifiers

   G Pillonnet, N Abouchi, R Cellier, A Nagari in 2009 IEEE International Symposium on Circuits and Systems (2009)

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4. A 0.12µm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz

   Bernhard Goll, Horst Zimmermann in Current (2007)

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5. A 0.13 μm CMOS 90 dB variable gain pre-power amplifier using robust linear-in-dB attenuator

   Yuta Araki, Toru Hashimoto, Shoji Otaka in 2008 IEEE Radio Frequency Integrated Circuits Symposium (2008)

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6. A 0.13μm CMOS adaptive sigma–delta modulator for triple-mode GSM/Bluetooth/UMTS applications

   Alonso Morgado, Rocío Del Río, José M De La Rosa, Rafael Castro-López, Belén Pérez-Verdú in Microelectronics Journal (2010)

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7. A 0 . 13-μm CMOS Digital Phase Shifter for K-band Phased Arrays

   Kwang-jin Koh, Gabriel M Rebeiz in Symposium A Quarterly Journal In Modern Foreign Literatures (2007)

   A 4-bit active digital phase shifter integrated with digital control circuitry in 0.13-mum CMOS technology is developed for K-band multiple antenna arrays. The active phase shifter synthesizes the required phase using a phase interpolation process…

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8. A 0 . 13μm CMOS Fully Differential Receiver with On-Chip Baluns for 60GHz Broadband Wireless Communications

   Chao-shiun Wang, Juin-wei Huang, Kun-da Chu, Chorng-kuang Wang in Science (2008)

   This paper presents a fully differential receiver with on-chip baluns for 60 GHz broadband wireless applications. This design consists of on-chip baluns, gm-boosted current-reuse low-noise amplifier (LNA), sub-harmonic dual-gate down conversion…

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9. A 0.13-µm CMOS local oscillator for 60-GHz applications based on push-push characteristic of capacitive degeneration

   Tino Copani, Hyungseok Kim, Bertan Bakkaloglu, Sayfe Kiaei in 2010 IEEE Radio Frequency Integrated Circuits Symposium (2010)

   A 60-GHz 10mW CMOS VCO is implemented together with a high-speed prescaler in a 130nm CMOS process. Compared to other push-push topologies, capacitive degeneration technique does not impact the resonator and switching transistors are re-used as…

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10. A 0.13 um SiGe BiCMOS technology featuring fT/fmax of 240/330 GHz and gate delays below 3 ps

    H Rucker, B Heinemann, W Winkler, R Barth, J Borngraber, J Drews, et al. in BCTM (2010)

    A 0.13 μm SiGe BiCMOS technology for millimeter-wave applications is presented. This technology features high-speed HBTs with peak transit frequencies fT of 240 GHz, maximum oscillation frequencies fmax of 330 GHz, and breakdown voltages BVCEO of…

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11. A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process

    G Van Der Plas, Stefaan Decoutere, S Donnay in 2006 IEEE International Conference Digest of Technical Papers SolidState Circuits (2006)

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12. A 0.18μm CMOS 300MHz Current-Mode LF Seventh-order Linear Phase Filter for Hard Disk Read Channels.

    X Zhu, Y Sun, J Moritz in Channels (2007)

    This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the…

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13. A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit

    G Hinton, M Upton, D J Sager, D Boggs, D M Carmean, P Roussel, et al. in IEEE Journal of Solid State Circuits (2001)

    This paper describes the main features and functions of the Pentium(R) 4 processor microarchitecture. We present the front-end of the machine, including its new form of instruction cache called the trace cache, and describe the out-of-order…

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14. A 0.18 μm CMOS TIA Plus Limiting Amplifier with a 5.3 GHz Overall Bandwidth for Fiber Optic Communications

    Matteo Pisati, Cristiano Bazzani, Francesco Gatta, Francesco Svelto, Rinaldo Castello in Analog Integrated Circuits and Signal Processing (2005)

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15. A 0.18 μm high dynamic range NTSC/PAL imaging system-on-chip with embedded DRAM frame buffer

    W Bidermann, A El Gamal, S Ewedemi, J Reyneri, H Tian, D Wile, in 2003 IEEE International SolidState Circuits Conference 2003 Digest of Technical Papers ISSCC (2003)

    The CMOS imaging system-on-chip includes an embedded frame buffer and operates at 100 MHz. The programmable chip produces color video at up to 500 frames/s with over 100 dB dynamic range using multi-capture. The sensor utilizes a 0.18 μm 1 P 4 M…

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16. A 0 . 1 8pim , 1 . 8-V CMOS High Gain Fully Differential Opamp Utilized in Pipelined ADC

    Ali Meaamar, Bin Othman in Response (2006)

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17. A 0.18- CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code

    S Hemati, A H Banihashemi, C Plett in IEEE Journal of Solid State Circuits (2006)

    Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. These decoders are used to efficiently decode the best known error correcting codes such as low-density parity-check (LDPC) codes and turbo codes. The…

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18. A 0.18um CMOS Bioluminescence Detection Lab-on-Chip

    H Eltoukhy, K Salama, A ElGamal in IEEE Journal of Solid State Circuits (2006)

    The paper describes a bioluminescence detection lab-on-chip consisting of a fiber-optic faceplate with immobilized luminescent reporters/probes that is directly coupled to an optical detection and processing CMOS system-on-chip (SoC) fabricated in a…

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19. A 0.18- m Dual-Gate CMOS Device Modeling and Applications for RF Cascode Circuits

    Hong-Yeh Chang, Kung-Hao Liang in IEEE Transactions on Microwave Theory And Techniques (2011)

    A merged-diffusion dual-gate CMOS device model is presented in this paper. The proposed large-signal model consists of two intrinsic BSIM3v3 nonlinear models and parasitic components. The parasitic elements, including the substrate networks, the…

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20. A 0.1% accuracy 100Ω-20mΩ dynamic range integrated gas sensor interface circuit with 13+4 bit digital output

    M Grassi, P Malcovati, A Baschirotto in Proceedings of the 31st European SolidState Circuits Conference 2005 ESSCIRC 2005 (2005)

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