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Papers in Communication

Communication papers in Electrical and Electronic Engineering, A

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Papers 1 - 20 of 1,728 in Communication, A
  1. The stereo audio DAC with novel single-ended class-D amplifier achieving a 103-dB SNR is fully integrated in a 65 nm CMOS technology. Novel asymmetric pulse-width modulation (PWM) is applied to minimize switching noise and nonlinearity in the…
  2. A photonic ADC based on balanced detection, phase encoded optical sampling, wavelength multiplexing, and electronic quantization is demonstrated. It achieves 7.0 ENOB resolution at a 2GSa/s sub-sampling rate for a 40 GHz input analog signal.
  3. This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength…
  4. A 2.4-GHz energy-efficient transmitter (TX) for wireless medical applications is presented in this paper. It consists of four blocks: a phase-locked loop (PLL) synthesizer with a direct frequency presetting technique, a class-B power amplifier, a…
  5. A 0.18μm CMOS MICS-band transceiver with a reconfigurable RF front-end is presented, reusing the same circuit core for super-regenerative wake-up receiver, receive-mode LNA, and transmit power amplifier, eliminating the need for an external…
  6. Anton, a massively parallel special-purpose machine for molecular dynamics simulations, performs a 32×32×32 FFT in 3.7 microseconds and a 64×64×64 FFT in 13.3 microseconds on a configuration with 512 nodes—an order of magnitude faster than all other…
  7. A lens-integrated EA/DFB laser was developed. Stable lasing operation and narrowly focused surface emission were achieved. In addition, 40-Gbit/s, 30-m error-free multimode fiber transmission was successfully demonstrated.
  8. This paper describes a multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture. Located at each mesh node is a five-port virtual cut-through…
  9. In this article, we present an efficient approach for the implementation of optimum maximum likelihood decoding of QPSK modulated multiple-input-multiple-output data streams. The proposed method does not compromise optimality of the detection…
  10. This paper presents a configurable MIMO detector with QR decomposition and channel interpolation for 4×4 MIMO-OFDM systems. QR decomposition (QRD) processor and MIMO detector are usually investigated independently in the literature; however, this…
  11. In this paper, VLSI implementation of a configurable, soft-output MIMO detector is presented. The proposed chip can support up to 8 × 8 64-QAM spatial multiplexing MIMO communications, which surpasses all reported MIMO detector ICs in antenna…
  12. Integration of mm-wave multiple-antenna systems on silicon-based processes enables complex, low-cost systems for high-frequency communication and sensing applications. In this paper, the transmitter and LO-path phase-shifting sections of the first…
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