We tested the hypothesis that single nucleotide polymorphisms (SNPs) within genes of the NF-κB pathway are associated with altered clinical outcome of septic shock patients. We genotyped 59 SNPs in the NF-κB pathway in a discovery cohort of septic…
Papers in Microprocessors
Microprocessors papers in Electrical and Electronic Engineering, A
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A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power…
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A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection,…
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A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-μm CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB…
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A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and…
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Switched-opamp (SO) techniques are explored to operate switched capacitor (SC) circuits in 1 V supply without on-chip voltage multiplier or low VT devices. However, the existing SO techniques require isolating the opamp from the signal path by…
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Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit…
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Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional…
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Page 1. 1 A 256kb - in 65nm CMOS by Benton Calhoun1 and Anantha Chandrakasan Massachusetts Institute of Technology
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A 2.6pJ/Inst subthreshold sensor processor designed for energy efficiency has been fabricated. A two-stage micro-architecture was implemented to mitigate the impact of process variation in subthreshold operation. Careful library cell selection and…
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A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm 2 core area with 1416-mW…
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In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) not only with homogeneous cores on regular mesh architecture as done by…
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As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip networks is becoming critically important. These networks face unique design…
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A 567 mm2 processor on 45 nm CMOS integrates 48 IA-32 cores and 4 DDR3 channels in a 6Ã4 2D-mesh network. Cores communicate through message passing using 384 KB of on-die shared memory. Fine-grain power management takes advantage of 8 voltage and 28…
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A 600-MHz single-chip multiprocessor, which includes two M32R 32-bit CPU cores , a 512-kB shared SRAM and an internal shared pipelined bus, was fabricated using a 0.15-μm CMOS process for embedded systems. This multiprocessor is based on symmetric…
Papers in associated sub-disciplines
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