Monitoring coral reef benthos with satellites has typically followed a "sensor-down" approach, with the classification algorithm driven by statistics derived from the imagery. I adopt a "reef-up" method, drawing on statistics derived from…
Papers in (Sub-)Surface Sensing Technologies and Systems
(Sub-)Surface Sensing Technologies and Systems papers in Electrical and Electronic Engineering, A
-
-
This paper presents a 10-bit 40-MS/s pipelined ADC in a 0.13-&x03BC;m CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling,…
-
A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are…
-
We propose a novel control method for lower- limb assist that produces a virtual modification of the mechanical impedance of the human limbs. This effect is accomplished through the use of an exoskeleton that displays active impedance. The proposed…
-
This brief presents an efficient and configurable multiple-input-multiple-output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 &x00D7; 2/3 &x00D7; 3/4 &x00D7; 4 MIMO and quadratic…
-
A micropower CMOS voltage-to-current converter is introduced which has a widely linear differential-input swing with a low signal-distortion with a minimum supply voltage of 1.2 V. This proposed circuit can achieve an almost rail-to-rail…
-
This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce…
-
Injection-locked quadrature voltage-controlled oscillators are introduced in this paper as high accuracy, low phase noise, and low-power I and Q generators. A master voltage-controlled oscillator (VCO), running at twice the output frequency, locks…
-
This paper presents a 10.0&x223C;11.5 Gb/s full-rate phase and frequency detector integrated with the clock recovery circuit (CRC) for application in optical receivers. A rotational phase and frequency detector (RPFD) without external reference…
-
This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital calibration techniques, comparator offset cancellation, a capacitor digital-to-analog converter (CDAC) linearity calibration, and internal clock control to…
-
A 10-bit 300 MSample/s pipelined analog to digital converter (ADC) using time-interleaved successive approximation register (SAR) ADC in the first stage is presented. By replacing the front-end pipelined stages with energy-efficient SAR-ADC, power…
-
A 10-bit 60-MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit is employed to enhance the dynamic performance of…
-
Data provided by large field of view optical sensors present a strong dependency on the source-target-sensor geometry. Despite substantial reduction of these bidirectional effects through the calculation of vegetation indices (VIs), residual impacts…
-
We aim at developing ultralight autonomous microflyers capable of navigating within houses or small built environments. Our latest prototype is a fixed-wing aircraft weighing a mere 10 g, flying below 2 m/s and carrying the necessary electronics for…
-
A CMOS operational amplifier that has a common-mode rejection ratio (CMRR), a power-supply rejection ratio (PSRR), and gain above 100 dB for each of these parameters is described. This is achieved by combining a high output-impedance tail current…
-
A CMOS operational amplifier with 110 dB CMRR/PSRR/gain is described. High CMRR is achieved using a cascoded input stage with high output impedance tail current source. A lateral PNP transistor and low-threshold voltage MOS transistor are used to…
-
This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential…
-
This paper reports a 128-channel neural recording integrated circuit (IC) with on-the-fly spike feature extraction and wireless telemetry. The chip consists of eight 16-channel front-end recording blocks, spike detection and feature extraction…
-
A 13.56 MHz RF transponder front-end circuit was designed for RFID or wireless sensor applications using 0.35-μm CMOS technologies. It converts RF power to DC and extracts clock and data; a smartly positioned NMOS device implements load…
-
A 16-bit 65-MS/s switched-capacitors pipeline analog-to-digital converter built in 0.45-mum 25-GHz fT complementary silicon-on-insulator BiCMOS delivers 80.1-dBFS signal-to-noise ratio, 98-dBc spurious-free dynamic range (SFDR) with 3-Vpp input…
Papers in associated sub-disciplines
Sign up today - FREE
Mendeley saves you time finding and organizing research. Learn more
- All your research in one place
- Add and import papers easily
- Access it anywhere, anytime