This paper presents a reconfigurable tri-level/multi-bit multi-mode ΔΣ modulator implemented in 0.13 μm CMOS. The modulator covers between 0.1 MHz and 20 MHz signal bandwidth which makes it suitable for cellular applications including 4G radio…
Papers in Telecommunications
Telecommunications papers in Electrical and Electronic Engineering, A
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In this paper we demonstrate a new technique that eliminates the impact of Kv nonlinearity by preserving the integral relationship of the VCO output phase to the input signal. Leveraging the VCO output phase directly precludes the need to span the…
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The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to…
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An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by…
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A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45 nm CMOS process, that achieves 0.45 pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations…
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A serial link transmitter fabricated in a large-scale integrated 0.4-μm CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the…
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This paper presents an inverter-based switched-capacitor integrator for 0.5 V low-voltage applications. The proposed integrator utilizing floating voltage source and forward body bias obtains high performance as well as good independence of…
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A 0.6-to-1 V inverter-based 5-bit flash ADC in 90 nm digital CMOS is presented. Single-ended comparators are formed using digital inverters and resistors. The comparators are designed for compatibility with nanoscale CMOS lithography. A single-ended…
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This paper presents an improved low-power DeltaSigma modulator, exploiting the class-C inverter and the feedforward topology. The measurement results show 14b dynamic range for a 20kHz bandwidth with 36muW power consumption from a 0.7V supply.
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This paper introduces a power-efficient, chopper-stabilized switched-capacitor sigma-delta (SigmaDelta) modulator that combines delayed input feedforward and single-comparator tracking multi-bit quantization to achieve high-precision, low-voltage…
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This paper discusses the design of an asynchronous analog-to-digital converter targeted for low-power sensing applications. The asynchronous sampling scheme will save power because it only samples the input signal when it is changing. The idea of…
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The wireless electronic nervous system interface known as the functional electrical stimulation-battery powered bion system is being developed at the Alfred Mann Foundation. It contains a real-time propagated wave micro-powered multichannel…
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This paper describes the results of an implementation of a high speed DeltaSigma ADC in 90 nm CMOS process, which is developed for a direct-conversion digital TV receiver. The DeltaSigma ADC is based on a switched-capacitor fourth-order single-loop…
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This paper describes a continuous time DeltaSigma modulator with 10MHz of bandwidth that achieves a DR of 87dB and an IMD of -91dBc while consuming 100mW.
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A variable-gain amplifier (VGA) with pseudo-random noise (PN) signal-dependent dithering and chopping is proposed. It allows the ADC gain and offset errors to be calibrated digitally in background. A 10~15 b 60 MS/s floating-point ADC (FADC) with…
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Floating-point analog-to-digital converter (FADC) utilizes an up-front variable-gain amplifier (VGA) to enhance its low-level resolution. Although it is a single-path system, varying gain by switching circuit elements in and out modulates the gain…
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An integrated low-noise amplifier, mixer, bandpass ΔΣ analog-to-digital converter (ADC), decimation filter, and two synthesizers implement a general-purpose back-end for a narrow-band superheterodyne receiver. The ΔΣ ADC is merged with the mixer and…
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An audio S.modulator achieves 105.5 dB dynamic range over 20 kHz audio bandwidth. A chopper stabilization technique is used in both the first integrator and the reference buffer to prevent degradation of the dynamic range and the peak…
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A second order sigma delta modulator (SDM) with a 5-bit quantizer has been presented using several novel techniques: simplified DAC arrays for easy implementation, high-order truncation noise shaping for increased tolerance to analog imperfections,…
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A second-order multibit bandpass ΣΔ modulator (BPΣΔM) used for the digitizing of AM/FM radio broadcasting signals at a 10.7-MHz IF is presented. The BPΣΔM is realized with switched-capacitor (SC) techniques and operates with a sampling frequency of…
Papers in associated sub-disciplines
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