A 0.021 m2 trigate SRAM cell with aggressively scaled gate and contact pitch

A 0.021 m2 trigate SRAM cell with aggressively scaled gate and contact pitch

by M A Guillorn, J Chang, A Pyzyna, S Engelmann, M Glodde, … E Joseph, R Bruce, J A Ott, A Majumdar, F Liu, M Brink, S Bangsaruntip, M Khater, S Mauer, I Lauer, C Lavoie, Z Zhang, J Newbury, E Kratschmer, D P Klaus, J Bucchignano, B To, W Graham, E Sikorski, V Narayanan, N Fuller, W Haensch show all authors

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2011 Symposium on VLSI Technology Digest of Technical Papers (2011)

Publisher: IEEE, Pages: 64-65

ISSN: 07431562
ISBN: 9784863481664

Abstract

We present the highest density demonstration of CMOS technology reported to date featuring a 6T SRAM cell size of 0.021 &x00B5;m2 (Fig. 1). The motivation for this work was to explore the limits of device patterning and basic module integration at dimensions relevant to the 10 nm node 1. A trigate device architecture with a minimum contacted gate pitch (CGP) and minimum contacted fin pitch (CFP) of 50 nm was used as the target technology for this demonstration.