A 0.13-amp;mu;m CMOS serializer for data and trigger optical links in particle physics experiments

doi:10.1109/TNS.2004.829551

A 0.13-amp;mu;m CMOS serializer for data and trigger optical links in particle physics experiments

by G Cervelli, A Marchioro, P Moreira

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2003 IEEE Nuclear Science Symposium Conference Record IEEE Cat No03CH37515 (2003)

Volume: 1, Issue: 3, Pages: 3-7

ISSN: 00189499
ISBN: 0780382579
DOI: 10.1109/TNS.2004.829551

Available from 2003 IEEE Nuclear Science Symposium Conference Record IEEE Cat No03CH37515

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Abstract

A 3.2-Gbit/s serializer prototype has been fabricated in a 0.13-μm CMOS technology to demonstrate its applicability within future Large Hadron Collider (LHC) data readout and trigger systems. The IC includes a clock-multiplying phase-locked-loop (PLL), a 50-Ω line driver, internal self-testing features, and data pattern generation. The serial output stream is 8 B/10 B encoded for compatibility with commercial receivers. Radiation hardening layout techniques have been adopted, which guarantee radiation tolerant operation inside the innermost LHC detectors over more than 10 yr. This paper describes the circuit architecture and reports on the experimental results. Signal quality (jitter, noise floor, eye opening) and bit-error rate (BER) are measured at different transmission rates using laboratory instrumentation and dedicated test beds.