An Oscilloscope Array for High-Impedance Device
Characterization

Fred Chen, Anantha Chandrakasan, Vladimir Stojanović
Department of Electrical Engineering
Massachusetts Institute of Technology
Cambridge, MA 02139
{fredchen,anantha,vlada}@mit.edu

Abstract— An equivalent time oscilloscope array is implemented
in a 90nm CMOS technology. A combination of adjustable
termination, calibration circuitry and capacitance compensation
enables driver bandwidths between 0.4 to 2GHz for termination
impedances of 20kΩ to 2kΩ for extraction of S-parameters and
delay characteristics of high impedance devices such as carbon
nanotubes (CNTs) and graphene. Measurement results show
that the capacitance compensation technique enhances the
bandwidth by 3X for impedances between 2kΩ and 20kΩ.
I. INTRODUCTION
Characterizing both DC and high-frequency characteristics of
nanoscale devices such as CNTs, graphene and nanowires is a critical
step in determining their viability for semiconductor applications [1].
Previous efforts to measure high frequency characteristics of CNTs
have been limited by a handful of common problems. First, the
traditional approach of using a network analyzer (VNA) to capture
the frequency response is limited by the poor power transfer between
the high impedance (>10kΩ) of the device and the 50Ω test
equipment termination. This impedance mismatch offsets the
selective bandwidth of the VNA used to reduce the noise floor,
resulting in a large variance of measured data due to signals being at
or near the noise floor. Second, measurement parasitics from test
probes and pads often dominate the reactance of the CNTs being
measured both limiting the accuracy of the results and the bandwidth
of the measurement. Third, given the dimensions of CNTs, test
setups are difficult to reproduce, limiting the range of lengths and
number of CNTs that can be measured.
To address these issues, we have developed an on-chip test
platform consisting of an array of 256 transceivers. Fig. 1 shows a
SEM image of the test-chip which is divided into two regions—a
higher termination impedance region (right) for long CNT/device
measurements and a lower termination impedance region (left) for
multi-wall CNT via or bundled CNT/device measurements. A
transceiver, whose layout is shown in the inset of Fig. 1, occupies a
100μm x 100μm area beneath each pad, and is independent of all
other transceivers allowing for measurements between any two pads
in the array. A capacitance compensation technique is used to allow
full sized 52μm square bond pads for device characterization at the
chip interface while maintaining input drive bandwidths up to 2GHz
for a 2kΩ termination. Each transceiver has an adjustable
termination, nominally between 2kΩ and 20kΩ, enabling better
power transfer by providing flexibility to match varying device
impedances. The adjustable termination used in conjunction with
several calibration circuits also enables direct measurement of
resistance and capacitance seen at the pad. Combined with several
on-chip test coupon transceivers that contain varying pad
components, these various measurement approaches aid in de-
embeding test setup parasitic from device measurements.
II. TRANSCEIVER ARCHITECTURE
A. System Architecture
Fig. 2 shows the top level block diagram of two transceivers
linked by a CNT ‘channel’. Similar to the technique used in [2] but
implemented with mostly on-chip components, the step response of
the channel is captured by changing the threshold voltage of the
sampler (VREF) and the relative phase of the receiver clock (RxClk)
with respect to the transmit clock (TxClk). Each transceiver is
capable of capturing the waveform at its input so both the launched
and received waveforms in a link can be captured simultaneously.
Fig. 3 highlights the measurement infrastructure and test setup for
the system. The sampler reference voltage (VREF) is provided by a
16-bit off-chip DAC which provides sub-mV voltage resolution. The
DAC also provides the sampler calibration voltage and drives the
reference currents for the chip. To get both good frequency
resolution and range, fine phase control over a long period is
required. To achieve this dynamic range, an external PLL with 6.5ps
delay steps feeds a 16-bit programmable clock divider to generate the
receive clock while the reference for the PLL feeds a similar clock
divider to drive the transmit clock. As shown in Fig. 3, rotating the
This research is funded in part by the Interconnect Focus Center, one of
five research centers funded under the Focus Center Research Program, a
Semiconductor Research Corporation Program.
PAD +
Metal-Metal
Caps for DAC
Filter
Scan Chain
Rx Counters
Tx Pipe
D
A
C
Tx
R
x
100 um
10
0
um
A
B
Fig. 1. SEM of the test chip (right) and a transceiver layout (left). Points A
and B indicate the link shown in the CNT measurement in section III

Fig. 2. Block diagram of 2 transceivers linked by a CNT and conceptual
waveforms captured by shifting VREF and RxClk