Asynchronous communications for NoCs

Abstract

Technology scaling beyond 90 nm drastically complicates the chip design process. Greater demand for higher performance and more functionality placed on a single chip, while maintaining power consumption at a reasonable level drives research towards new architectural and communication paradigms that support topological scaling. Network-on-Chip is seen as one such paradigm, but its inherently massive parallelism and distribution of switching activity naturally lead to a much wider spectrum of techniques used for system timing. The use of global clocking becomes very difficult for improving power and performance while at the same time keeping acceptable levels of robustness to faults, both fabrication and run time, as well as to the increasing parametric variability of components. Systems based on NoCs are thus becoming more diverse in terms of timing, and if not fully asynchronous, then mixed, e.g. globally asynchronous and locally synchronous. The notion of timing and synchronization is pervasive in system communication architectures and affects all layers of hierarchy, but its biggest effect is probably at the link layer, where the notion of data validity in communication channels between processing nodes and network routers is paramount. This chapter provides an overview of the various asynchronous techniques that are used in such links, including signalling schemes, data encoding and synchronization solutions. Those are discussed with a view of comparison in terms of area, power and performance. The fundamental issues of the formation of data tokens based on the principles of data validity, acknowledgement, delay-insensitivity, timing assumptions and soft-error tolerance are considered. The chapter also covers some of the aspects related to combining asynchronous communication links to form parts of the entire network architecture, which involves asynchronous logic for arbitration and routing hardware. To this end, we also present basic techniques for building small-scale controllers using the formal models of petri nets and signal transition graphs. © 2011 Springer Science+Business Media LLC.