Fred Chen2, Hei Kam1, Dejan Markovic3, Tsu-Jae King Liu1, Vladimir Stojanovic2, Elad Alon1
1Department of EECS, University of California, Berkeley, CA 94720, USA
2Department of EECS, Massachusetts Institute of Technology, Cambridge, MA 02139, USA
3EE Department, University of California, Los Angeles, CA 90095, USA


Abstract—To overcome the energy-efficiency limitations
imposed by finite sub-threshold slope in CMOS transistors, this
paper explores the design of integrated circuits based on nano-
electro-mechanical (NEM) relays. A dynamical Verilog-A
model of the NEM relay is described and correlated to device
measurements. Using this model we explore NEM relay design
strategies for digital logic and I/O that can significantly
improve the energy efficiency of the whole VLSI system. By
exploiting the low effective threshold voltage and zero leakage
achievable with these relays, we show that NEM relay-based
adders can achieve an order of magnitude or more
improvement in energy efficiency over CMOS adders with ns-
range delays and with no area penalty. By applying
parallelism, this improvement in energy-efficiency can be
achieved at higher throughputs as well, at the cost of increased
area. Similar improvements in high-speed I/O energy are also
predicted by making use of the relays to implement highly
energy-efficient digital-to-analog and analog-to-digital
converters.
I. INTRODUCTION
Despite the drastic improvements in performance, cost, and
energy efficiency brought by CMOS technology scaling over the
last 40 years, integrated circuits today are severely limited by their
total power consumption. The issue has been exacerbated recently
because threshold voltages have already hit the point at which they
optimally balance the leakage and dynamic energy consumption of
a design. Thus, further supply scaling comes at the expense of per-
core performance, and it is this trend that has forced the move to
chip-multiprocessors.
Unfortunately, even this parallelism will eventually become
ineffective since the energy efficiency achievable by CMOS
transistors is limited by their sub-threshold leakage. This is due to
the fact that in the sub-threshold regime of operation, an increase in
the threshold voltage (Vth) decreases the leakage current by exactly
the same amount it increases the delay. This makes the energy per
operation of a CMOS functional unit level off to a defined
minimum level [1] no matter how slowly the circuit is allowed to
run. Thus, if a device with significantly improved leakage
characteristics (i.e., steeper sub-threshold slope) were available,
major improvements in energy efficiency over CMOS could be
achieved.
Many researchers are therefore exploring new switching device
concepts [2,3] to achieve sub-threshold slopes steeper than the limit
set by kBT/q in field-effect or bipolar junction transistors.
However, many of these devices are based on tunneling and hence
have very low on-state current at low supply voltages. In order to
significantly improve upon the energy-efficiency of CMOS, an
alternative switching device which offers extremely low off-state
current together with relatively high on-state current at low supply
voltages is needed. In other words, the device should behave as
closely as possible to an ideal switch.
In this paper we focus on electrostatically actuated mechanical
switches (similar to those described in [4]) because they offer
nearly ideal switching characteristics (zero leakage, infinitely steep
sub-threshold slope) and are more scalable and compatible with
conventional micro/nanofabrication processes than relays that are
actuated thermally, magnetically, or piezoelectrically. Specifically,
we consider a 4-terminal relay design which guarantees that the
state of the switch is determined only by the voltage difference
between a movable gate terminal and a fixed body terminal. The
time required to mechanically displace such a relay from the off- to
the on-state is in the nanosecond range, while the electrical time
constant required to charge and discharge the parasitic capacitance
of a single relay is on the order of single picoseconds or less.
Despite the large mechanical delay, we show that NEM relays
can be useful for a wide range of VLSI applications by re-
examining traditional system- and circuit-level design techniques to
take advantage of the electrical properties of the device. Unlike
CMOS circuit design, logic functions should be implemented as a
single complex gate with minimum-sized relays, resulting in
significantly reduced logic complexity. We show that for
throughputs in the ~100 MOPS range, relay-based circuits can be
over 10x more energy-efficient than CMOS designs without any
area penalty. Furthermore, by trading off increased area in order to
apply parallelism to relay-based functional blocks, these energy-
efficiency benefits can be extended to throughputs greater than
1 GOPS with ~6-25x larger area compared to CMOS. We also
show that this improved energy efficiency in digital logic can be
extended to the I/O’s at the same rate. Although the lack of a
“saturated” region of operation at first seems like a significant
roadblock to analog/mixed-signal design with NEM relays, we
show that highly energy-efficient DAC and ADC structures can be
built using the relay purely as a switching element.
To further elucidate the characteristics of these switches and
substantiate the subsequent simulation results, in Section II we first
describe the structure and operation of the relay design used in this
paper, followed by the device model used for the circuit
evaluations. Subsequently, since digital logic and I/O are key
building blocks required to implement a potential NEM relay VLSI
system, we next describe in Sections III and IV relay-based design
strategies for these components.
II. OVERVIEW OF NEM RELAYS
A. Structure and Operation
Fig. 1 shows cross-sectional and top (layout) views of a NEM
relay device suitable for VLSI circuits. The metallic conducting
channel is attached via an insulating gate dielectric to the cantilever
gate electrode. In the off-state (|Vgb| < Vth), an air gap separates the
channel from the metallic source and drain electrodes so that no
current can flow. In the on-state (|Vgb| ≥ Vth), electrostatic force
bends the cantilever beam sufficiently to bring the channel into
contact with the source/drain electrodes in the dimple regions,
providing a conductive path for current to flow. Since the relay
switches on abruptly as |Vgb| is increased above Vth, the Id-Vgb
Integrated Circuit Design with NEM Relays