A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors

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Abstract

The globally asynchronous locally synchronous (GALS) design style for a large area chip has become increasingly attractive due to the difficulty of designing global clocking circuits at high clock frequencies in the GHz range. In this paper, we present a high-speed interconnect network for a GALS multiprocessing system composed of a 2-D mesh array of processors. Processors are locally clocked by their own oscillators and communicate together using a static circuit-switched technique combined with a source-synchronous communication scheme. A technique to maximize the timing reliability on long-distance interconnects at high clock rates is proposed that is area and power efficient with low latency and allows a sustained ideal peak throughput of one word per cycle. ©2009 IEEE.

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Tran, A. T., Truong, D. N., & Baas, B. M. (2009). A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 996–999). https://doi.org/10.1109/ISCAS.2009.5117926

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