A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS

Abstract

System-on-chips (SoCs) are being widely adopted in mobile applications, and are driven by the need for longer battery life, their power budget continues to decrease. In addition, the phase-locked loop (PLL) for the SoC host clock has to be a very low power circuit to support the always-on always-connected (AOAC) feature for SoCs integrated into hand-held devices. The proposed PLL, implemented in a high-k metal-gate 32nm logic CMOS technology, provides process scalability to the next process technology node, uncompromised system response, and loop stability under process variation and minimum power envelop constraints. As the jitter requirements for the host clocking PLL are not stringent, the proposed architecture emphasizes the power efficiency over the jitter performance. © 2011 IEEE.