1270 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2003
Short Papers_______________________________________________________________________________
Static Timing Analysis for Level-Clocked Circuits
in the Presence of Crosstalk
Soha Hassoun, Christopher Cromer, and Eduardo Calvillo-Gámez
Abstract—Static timing analysis is instrumental in efficiently verifying a
design’s temporal behavior to ensure correct functionality at the required
frequency. This paper addresses static timing analysis in the presence of
crosstalk for circuits containing level-sensitive latches, typical in high-per-
formance designs. The paper focuses on two problems. First, coupling in a
sequential circuit can occur because of the proximity of a victim’s switching
input to any periodic occurrence of the aggressor’s input switching window.
This paper shows that only three consecutive periodic occurrences of the
aggressor’s input switching window must be considered. Second, an ar-
rival time in a sequential circuit is typically computed relative to a specific
clock phase. The paper proposes a new phase shift operator to align the ag-
gressor’s three relevant switching windows with the victim’s input signals.
This paper solves the static analysis problem for level-clocked circuits itera-
tively in polynomial time, and it shows an upper bound on the number of it-
erations equal to the number of capacitors in the circuit. The contributions
of this paper hold for any discrete overlapping coupling model. The exper-
imental results demonstrate that eliminating false coupling allows finding
a smaller clock period at which a circuit will run.
Index Terms—Crosstalk, design automation, timing, timing circuits, very
large scale integration.
I. INTRODUCTION
Shrinking process geometries have imposed new challenges in both
design and verification. One particular problem is the capacitive cou-
pling among two or more signals in the circuit. Coupling exists due
to the proximity of a wire to others that are either in the same layer
(lateral coupling) or in different layers (interlayer coupling). Coupling
creates undesired noise and delay in the circuit. This phenomenon is
commonly referred to as crosstalk.
Noise on a signal refers to creating voltage deviation from the nom-
inal supply and ground rails when the signals should otherwise have
been stable at a high or low value as dictated by the logic and delay of
the circuit [21]. Noise greater than the allowed noise margins causes
malfunctions.
Delay variation due to capacitive coupling refers to either speeding
or slowing the point in time where a switching net reaches its receiving
threshold, thus causing receiving gates in the immediate fanouts to
switch sooner or later than expected. The delay variation is depen-
dent on the relative arrival times of the victim net and the aggressor(s)
net(s) that capacitively couple to the victim. If the victim is switching
in the same direction as the aggressor(s), then we have assistive cou-
pling, and the victim switches sooner than anticipated. Delay improve-
ments could potentially cause race-through or double-clocking condi-
tions, and, thus, circuit failure. With opposing coupling, the victim net
switches later due to opposing transition on the aggressor(s). Delay
Manuscript received January 15, 2002; revised August 16, 2002. This work
was supported by National Science Foundation POWRE and CAREER grants.
This paper was recommended by Associate Editor M. Papaefthymiou.
S. Hassoun and E. Calvillo-Gámez are with the Computer Science Depart-
ment, Tufts University, Medford, MA 02155 USA (e-mail: soha@cs.tufts.edu).
C. Cromer is with the Infineon Technologies Corporation, San Jose, CA
95512 USA.
Digital Object Identifier 10.1109/TCAD.2003.816209
degradation causes performance failure; the circuit will not run at the
desired frequency. Static timing analysis techniques, which verify a de-
sign’s temporal behavior to ensure correct functionality at the required
frequency, must thus consider the effects of crosstalk.
Several static timing analysis techniques that consider crosstalk have
been proposed for combinational circuits. Some are based on iterative
techniques [3], [18]; some are based on the propagation of events [5];
others are based on more complex mathematical formulations [10].
The choice of what constitutes coupling (any overlap of the inputs’
switching windows v.s. more detailed coupling conditions) affect the
complexity of the algorithms. Consideration of the functional correla-
tion of the victim and the aggressors allows further accuracy in analysis
[2], [4], [25]. The worst case victim delay can be obtained by driver
modeling using reduced order modeling and worst case alignment of
the aggressors relative to the victim [7], [9], [22].
This paper addresses crosstalk analysis for circuits with level-sensi-
tive latches. Level-clocked circuits are certainly dominant in high-per-
formance designs because they can operate at faster clock rates than
edge-triggered circuits [8]. This is because, unlike edge-triggered regis-
ters, latches allow borrowing time across their boundaries. Researchers
have efficiently solved the problem of verifying a clock schedule [11],
[14], [23]. However, naively assuming worst case crosstalk while run-
ning these algorithms yields pessimistic clock periods.
A clock schedule specifies the clock period and the relative timing
and duration of each of the phases in the schedule. Given a circuit and
a clock schedule, we solve the problem of clock schedule verification
in the presence of crosstalk. That is, we answer the following question.
Does the circuit run at the specified clock period given the phase wave-
forms imposed by the clock schedule?
The difficulty of the clock-schedule verification problem is twofold.
First, due to the periodic nature of signals in a sequential circuit, cou-
pling can occur because of the proximity of a victim’s switching input
to any periodic occurrence of the aggressor’s input switching window.
More than one occurrence of the aggressor waveform must thus must
be compared against that of the victim. Second, the arrival times in a
level-clocked circuit are typically computed relative to a specific clock
phase. Translating the arrival times using a common reference point
will be needed to meaningfully compare the switching windows.
This paper addresses both of these problems. We show that only
three consecutive switching windows of the aggressor’s input must
be compared with the victim’s input switching window. To determine
overlap in switching windows at the inputs of the victim and aggressor,
we propose a phase shift operator that can translate values from the
aggressor’s to the victim’s time zones. The paper solves the clock-
schedule verification problem in the presence of crosstalk iteratively in
polynomial time. Furthermore, it shows an upper bound on the number
of iterations equal to the number of capacitors in the circuit.
Several discrete and continuous coupling models are possible for
representing the change in delay due to coupling. We choose to use the
dynamically bounded delay model [10], an abstract delay model that
allows a gate’s delay to be assigned one of many values depending on
related operating conditions. While more accurate continuous models
are possible, e.g., [6], the chosen model is a generalization of discrete
coupling models, such as ones that assume a 0 X, 1 X, or 2 X increase
in delay, e.g., [18]. While suffering from inaccuracies compared with
continuous models, discrete models require less computational com-
plexity. Furthermore, they have proved helpful in understanding the
0278-0070/03$17.00 © 2003 IEEE