A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.
CITATION STYLE
Alves, G. R., & Martins Ferreira, J. M. (1999). System verification strategy based on the BST infrastructure. Proceedings - IEEE International Symposium on Circuits and Systems, 1. https://doi.org/10.1109/iscas.1999.777799
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