VLSI Design And Analysis Of Low Power 6T SRAM Cell Using Cadence Tool
CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity. Static RAM used in battery operated devices required less area and low power consumption. Static RAM used in processors needs less read and write timing. We start SRAM cell design with two objectives, first to lower the operating voltage from 3V to 1.8V. Second to reduce active and static power consumption for battery operated application. But it has been observed that the stability of cell is seriously affected by the decrease in supply voltage (Vdd). By optimizing the cell ratio of the cell and improving the precharge circuitry we can achieve these goals. For a stable operation of cell, cell ratio must be in order to 1.5 -2, along with the pull up ratio lower than the 1.8. These ratios are standard for .25u technology . In 0.18 micron technology these ratio is varied for getting desired performance. One new technique is used for reducing the power of the memory cell while maintaining the stability. Although this technique is discussed in. But the stability of cell was not coming satisfactory. Some other work also been published in literature for low power and High Speed SRAM. But most of the work is done on peripheral circuitry for reducing the power and increasing the speed. Further the paper is structured as follows. First the designing of 6T SRAM cell is shown with conventional bitlines. Than 6T with short buffered bitline is presented for reducing both power consumption and delay. Thirdly the stability of cell is measured and layout of the cell is shown. Finally the paper is concluded and future work is discussed.