The resolution of multi-bit linear TDC is closely related to process technology since the minimum resolvable time quantity is proportional to one-inverter delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3]. Since the time resolution is determined by the difference between two inverter delays, a large number of inverter stages is required to cover a large detection range, resulting in long conversion time and high power consumption. Well-established data-conversion architectures have also been sought to achieve both large detection range and high resolution [4,5]. The two-step TDC was proposed to improve both the resolution and detectable range by amplifying the time residue after the coarse conversion for the fine conversion [4]. But, the previous time amplification schemes [4, 6] use metastability and suffer from small input range and gain uncertainties due to nonlinearity and PVT variations. This paper presents a power-efficient and wide dynamic range sub-exponent TDC. Based on a cascaded chain of 2x time amplifiers, the TDC generates the exponent-only information for the fractional time difference. ©2010 IEEE.
CITATION STYLE
Lee, S. K., Seo, Y. H., Suh, Y., Park, H. J., & Sim, J. Y. (2010). A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18μm CMOS. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 53, pp. 481–483). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/ISSCC.2010.5433837
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