A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging

Abstract

A 45nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153Mb SRAM arrays with SRAM cell size of 0.346 μm2, and on multiple microprocessors. © 2007 IEEE.