This paper describes a multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 6 × 4 2D-mesh network-on-chip architecture. Located at each mesh node is a five-port virtual cut-through packet-switched router shared between two IA-32 cores. Core-to-core communication uses message passing while exploiting 384 KB of on-die shared memory. Fine grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1 V supply, the cores operate at 1 GHz while the 2D-mesh operates at 2 GHz. As performance and voltage scales, the processor dissipates between 25 W and 125 W. The 567mm2 processor is implemented in 45 nm Hi-K CMOS and has 1.3 billion transistors. © 2006 IEEE.
CITATION STYLE
Howard, J., Dighe, S., Vangal, S. R., Ruhl, G., Borkar, N., Jain, S., … Van Der Wijngaart, R. (2011). A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling. In IEEE Journal of Solid-State Circuits (Vol. 46, pp. 173–183). https://doi.org/10.1109/JSSC.2010.2079450
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