Performance Evaluation of Different Topologies of SRAM and SRAM Memory Array Design at 180nm Technology

Abstract

Memory circuits such as static random-access memory (SRAM) and dynamic random-access memory (DRAM) form an integral part of system design and contribute significantly to system-level power consumption. Memory operating speeds and power dissipation have become important parameters due to the explosive growth of battery-operated appliances and the increased integration of circuits Hence SRAMs with different topologies are examined in terms of parameters like propagation delay, Static Noise Margin (SNM), corner analysis, and static power dissipation by simulating using versatile tool cadence virtuoso at 180nm technology. Besides, topological performance comparison, the SRAM memory array has also been illustrated from 2×2, 4×4 to 8×8, thereby verifying the read and write modes of operation of SRAM.