Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

Abstract

This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is 61°, the total power dissipation is 0.91mW, the output voltage swing is from -0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94nV√Hz. at 1MHz, the positive slew rate is 11.37V/μs, the negative slew rate is 11.39V/μs, the settling time is 137ns, the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at ±1V and ±0.814V power supplies' voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.