A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support. © 2012 by the authors; licensee MDPI, Basel, Switzerland.
Ou, C. M., Li, H. Y., & Hwang, W. J. (2012). Efficient K-winner-take-all competitive learning hardware architecture for on-chip learning. Sensors (Switzerland), 12(9), 11661–11683. https://doi.org/10.3390/s120911661