The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of 3D MEMS and wafer-level packaging. The fabrication process relies on wafer stacking by hydrophilic direct bonding of plasma activated Si/SiO2 surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid low temperature bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. Further, the technology is fully compatible with waferlevel packaging approaches based on through silicon vias (TSV) or CMOS/MEMS integration. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.
Kühne, S., & Hierold, C. (2010). Hybrid low temperature wafer bonding and direct electrical interconnection of 3D MEMS. In Procedia Engineering (Vol. 5, pp. 902–905). Elsevier Ltd. https://doi.org/10.1016/j.proeng.2010.09.255