Efficient FPGA implementation of RSA coprocessor using scalable modules

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RSA Cryptosystem is considered the first practicable secure algorithm that can be used to protect information during the communication. The significance of high security and efficient implementations of RSA have formed the base of many cryptographic engineering researches. In fact, the implementation of RSA Cryptosystem is heavily based on modular arithmetic and exponentiation involving large prime numbers. In this paper, we propose an efficient FPGA design and architecture for RSA cryptosystem using ALTERA FPGA Hardware Kit. The proposed design comprises six levels: random two prime numbers, parallel multiplication of the prime numbers and their decremented values, get encryption key, get decryption key, encryption and decryption levels. As the modular multiplication is considered as the heart of RSA computations, Interleaved Algorithm was particularly chosen as an efficient solution to speed up the modular multiplication. The experimental part of this work has been synthesized for both ALTERA Cyclone IV EP4CE115F29C7 and VERTIX VII VC707 FPGA kits and resulted in a maximum frequencies of 15.725 MHz, 17.629 MHz respectively. These findings make our design comparable and a good choice for efficient RSA Cryptoprocessor design. The results for the FPGA implementation for EC design using these curves is also proposed in this paper. © 2014 Elsevier B.V.




Al-Haija, Q. A., Smadi, M., Al-JA’Fari, M., & Al-ShuA’Ibi, A. (2014). Efficient FPGA implementation of RSA coprocessor using scalable modules. In Procedia Computer Science (Vol. 34, pp. 647–654). Elsevier B.V. https://doi.org/10.1016/j.procs.2014.07.092

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