Phosphorus gettering of impurities at low-temperature annealing for enhancing the performance of P-type PERC

Abstract

We demonstrate that the phosphorus diffusion gettering (PDG) process including low-temperature gettering with the emitter present at 400 °C under different annealing times can improve the performance of p-type passivated emitter and rear cells (PERCs). Moreover, symmetrical sample structures that are the same as the rear side of the PERC are also fabricated to determine the intrinsic electrical and interfacial properties of the remaining defects of the silicon wafer after the gettering layer is etched off. As a result, all I-V parameters of gettered PERCs are improved, and the same trend is observed for the minority carrier lifetime and implied open-circuit voltage values of the symmetrically passivated samples with dielectric layers. The results of internal quantum efficiency for gettered PERCs show notable improvements for both short- and long-wavelength photons, indicating better silicon bulk quality and a higher level of surface passivation upon low-temperature gettering. Accorded to the results obtained in this study, a greater enhancement in gettering efficiency is more likely attributed to the internal gettering mechanism through the rearrangement of remaining dissolved impurities, either within the silicon bulk or at the wafer interfaces. In particular, the latter case leads to the redistribution of interface states that determine the final level of surface passivation. Since the photoluminescence (PL) imaging technique was also used to confirm the carrier recombination activity after cell processing, the enhancement of PL intensities for gettered PERCs confirms the effectiveness of low-temperature gettering (400 °C) after PDG in removing and rearranging impurities in the silicon wafer. The results presented in this study demonstrate that low-temperature gettering with the emitter present can be applied at the cell level to enhance the electrical properties and yield of PERC solar cells.