Modified low-power multiplier architecture

Abstract

In this paper, we have implemented a modified version of the Bypass Zero Feed A Directly (MODBZ-FAD) multiplier architecture based on shift- and add- method. This architecture has considerably low power than the other multiplier architectures. In this architecture we have reduced the power consumption and propagation delay of the circuit. This has been done by removing Bypass register,dflipflop & multiplexers. The synthesis results shows that the switching activity had been lowered up to 78% and power consumption up to 22% when compared up to BZ-FAD architecture. © 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering.