Verification of all-digital SPARC instruction set based on FPGA

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Due to the closeness of an embedded system, to test in the embedded software is extremely difficult, especially for real-time embedded software. It is no doubt that instruction set simulation(ISS) system based on embedded SoC will greatly reduce difficulties of embedded software testing. Therefore, to make sure the credibility of the instruction set simulation system it is especially important. The huge number of random test cases generated during testing makes it unable to determine the running results. A method of hardware and software collaborative verification based on FPGA Leon core and microcomputer software SPARC instruction set is proposed to solve both the efficiency in traditional software testing and the accuracy in determining running results problems effectively. Ten test cases from the Mibench standard test set are selected for hardware and software collaborative verification. The statistical results show the instruction coverage of all-digital SPARC V8 simulator reaches 97 percent. © 2011 Published by Elsevier Ltd.




Cui, K., Zhou, K. J., Wang, J., Hao, S., & Lin, C. (2012). Verification of all-digital SPARC instruction set based on FPGA. In Procedia Engineering (Vol. 29, pp. 1276–1280).

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