Challenges in Electron Beam Lithography of Silicon Nanostructures

Abstract

The fabrication of semiconductor nano-structures is one of the most important tools for microelectronic research. Due to the high gate coupling achieved in nanowires, they provide an excellent vehicle for the demonstration of emerging semiconductor devices. Top-down fabrication has been shown vital in terms of alignment, uniformity, and flexibility of the fabricated structures. In this work we review the most important challenges in Electron Beam Lithography patterning for semiconductor nano-structures and exemplify them on our own laboratory results. Electron beam lithography processes on Silicon-On-Insulator substrates are discussed, which yield horizontal and vertical nanowires, as well as special research structures, such as Hall bars. Measures are given to analyze and diminish undesired effects like proximity and line-edge roughness. As an example of how these measures can be successfully employed, we show a reconfigurable field effect transistor built on a dense nanowire array.