A High-Performance Full Adder Design with Low Area, Power and Delay

Abstract

A new one-bit adder architecture is described that may be used with a variety of logics, including Static CMOS, transmission gates, the Transmission Full Adder (TFA), and the New-14T Gate Diffusion Input Method (GDI). The Modified Gate Diffusion Input Method (MGDI) is used to suggest a novel structure design for a full adder. The full adder circuit is used in the Modified Gate Diffusion Input Method (MGDI), and experimental results demonstrate its superior performance compared to traditional methods. Full adders with multistage arrangements are also considered, as their performance may differ from that of a 1-bit full adder. As a result, two applications of multistage full adder structures, the ripple carry adder (RCA) and 6:2 compressor are used to analyze the findings. The power, area and delay are reduced by around 40% when compared to the existing methods. All the designs are simulated using Tanner EDA. The proposed full adder has a lower transistor count (6 or 7 transistors), lower power dissipation, and less delay than previous designs, according to simulation data.