Hybrid-gate MoS2 2T0C DRAM for low-power multi-bit storage with high linearity

Abstract

With the increasing demand for high-performance computing, 2T0C DRAM has been extensively studied for its high integration density, low power consumption and non-destructive readout. Two-dimensional (2D) semiconductors, with ultra-low leakage current, improve the retention characteristics but face limitations in conventional 2D-based 2T0C cells: the subthreshold operation of positive-threshold transistors at low write voltages reduces read current, introduces nonlinearity, and degrades robustness, and thus requires higher write voltages and increased power consumption. To address this, we propose a hybrid-gate MoS2 2T0C DRAM, where a low-leakage Au-gate transistor serves as the write node and a depletion-mode Al-gate transistor functions as the readout node. The device achieves >100 s retention time and reduces the minimum write voltage to 0.2 V, enabling distinguishable 3-bit storage. Furthermore, a 32 × 32 MoS2 2T0C DRAM circuit demonstrates image storage and readout capabilities with <5% bit error rate after 600 s, highlighting its potential for future high-density, low-power memory applications.