Effect of adding DC-offset estimation integrators in there-phase enhanced phase-locked loop on dynamic performance and alternative scheme

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Abstract

Three-phase enhanced phase-locked loop (3P-EPLL) can estimate the amplitude, frequency and phase angle of the positive sequence of the three-phase inputs without using a synchronous reference frame. However, the presence of DC offsets in the inputs of the conventional 3P-EPLL introduces a periodic ripple in the estimated information. Thus, DC-offset estimation integrators (DCEIs) to estimate and feedback the DC component as an error signal are introduced in 3P-EPLL to eliminate the disturbance. This study presents a comprehensive study of the transient performance of 3P-EPLL with DCEIs, proving that a worse and longer dynamic period is caused by the coupling of the frequency and amplitude loop resulted from DCEI. Further, a hybrid filtering 3P-EPLL based on delayed-signal cancellation to reject the DC component and sliding Goertzel transform-based filter to eliminate the effect of harmonics and unbalanced inputs is proposed. Thus, a correct estimation is achieved even under unbalanced inputs with both DC and harmonic components. A set of detailed experiments of the former three enhanced phase-locked loops (EPLLs) are presented to display the deficit of the conventional EPLLs and better performance of the proposed scheme.

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Wu, F., Zhang, L., & Duan, J. (2015). Effect of adding DC-offset estimation integrators in there-phase enhanced phase-locked loop on dynamic performance and alternative scheme. IET Power Electronics, 8(3), 391–400. https://doi.org/10.1049/iet-pel.2014.0317

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