A Low-Power and Low-Voltage Power Management Strategy for On-Chip Micro Solar Cells

Abstract

Fundamental characteristics of on-chip micro solar cell (MSC) structures were investigated in this study. Several MSC structures using different layers in three different CMOS processes were designed and fabricated. Effects of PN junction structure and process technology on solar cell performance were measured. Parameters for low-power and low-voltage implementation of power management strategy and boost converter based circuits utilizing fractional voltage maximum power point tracking (FVMPPT) algorithm were determined. The FVMPPT algorithm works based on the fraction between the maximum power point operation voltage and the open circuit voltage of the solar cell structure. This ratio is typically between 0.72 and 0.78 for commercially available poly crystalline silicon solar cells that produce several watts of power under typical daylight illumination. Measurements showed that the fractional voltage ratio is much higher and fairly constant between 0.82 and 0.85 for on-chip mono crystalline silicon micro solar cell structures that produce micro watts of power. Mono crystalline silicon solar cell structures were observed to result in better power fill factor (PFF) that is higher than 74% indicating a higher energy harvesting efficiency.