Design of Low Power 6T Sram with and without ROFs

Abstract

An aggressive scaling in size and the increasing number of the transistor count are the important challenge of the design of Integrated Circuit (IC). In the same manner interconnection lines and resistive opens also became a major problem in present nanometer technology. The resistive open faults [ROFs] represent degradation [1] in connectivity’s within a circuit’s interconnections because of unavoidable manufacturing failures present in both current and future developing technologies. The resistive open fault [ROF] is an imperfect circuit connection that can be modelled as a defect resistors between two nodes of the circuit. The Resistive open faults [2] not causes the functionality of the circuit instantly. But, it causes the delay faults. In this research proposal, the impact of resistive open faults measured in 6-Transistors (6T) Static RAM memory cell design. The proposed 6T Static RAM memory cell implemented in 45nm technology by using Cadence Virtuoso library. The main goal of this proposed research work is to analise the effect of resistive open faults and how it reduce delay and power of 6T Static RAM cell. The resultant outputs of proposed 6T SRAM cell operation with and without ROFs will be compared.