Quantitative Analysis of Hole-Trapping and Defect-Creation in InGaZnO Thin-Film Transistor under Negative-Bias and Illumination-Stress

Abstract

© The Author(s) 2014. We report two measurement methods, named positive gate pulse mode (PGPM) and double sweeping mode (DSM), which can estimate the hysteresis induced by hole trapping in a gate insulator (Δ Vhole) and by defect creation in the IGZO channel (ΔVdefect). The effects of IGZO deposition temperature and of stress temperature on defect creation in the channel under negative bias and illumination stress (NBIS) are investigated. The results show that high deposition temperature of IGZO reduces defect creation in the channel under NBIS. The average activation energy for hole trapping in a GI under NBIS has been calculated to be 0.39 eV. The results of PGPM and DSM measurement are valuable for the further progress in the work to improve NBIS reliability of IGZO TFT.