Self-reconfigurable architectures for HEVC Forward and Inverse Transform

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Abstract

This work introduces a run-time reconfigurable system for HEVC Forward and Inverse Transforms that can adapt to time-varying requirements on resources, throughput, and video coding efficiency. Three scalable designs are presented: fully parallel, semi parallel, and iterative. Performance scalability is achieved by combining folded/unfolded 1D Transform architectures and one/two transposition buffers. Resource usage is optimized by utilizing both the recursive even–odd decomposition and distributed arithmetic techniques. The architecture design supports video sequences in the 8K Ultra High Definition format (7680 × 4320) with up to 70 frames per second when using 64 × 64 Coding Tree Blocks with variable transform sizes. The self-reconfigurable embedded system is implemented and tested on a Xilinx® Zynq-7000 All-Programmable System-on-Chip (SoC). Results are presented in terms of performance (frames per second), resource utilization, and run-time hardware adaptation for a variety of hardware design parameters, video resolutions, and self-reconfigurability scenarios. The presented system illustrates the advantages of run-time reconfiguration technology on PSoCs or FPGAs for video compression.

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APA

Llamocca, D. (2017). Self-reconfigurable architectures for HEVC Forward and Inverse Transform. Journal of Parallel and Distributed Computing, 109, 178–192. https://doi.org/10.1016/j.jpdc.2017.05.017

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