Abstract
A 0.5 micron BiCMOS process that has been developed at HP is used to illustrate the details in process design needed as a prerequisite for success in manufacturing. An existing CMOS process was used as the core for building up the BiCMOS process. CMOS design rules and performance could not be altered by the addition of the bipolar processes. Issues related to bipolar integration, individual process modules, interactions between CMOS and bipolar, and manufacturability are discussed in detail. NPN bipolar devices with fτ > 15GHz @ IV Vce and BVceo >6V have been obtained. This process has been targeted to be used in building future high performance ASIC products.
Cite
CITATION STYLE
Lau, C. K., Lin, C. H., & Packwood, D. L. (1992). Sub-micron BiCMOS process design for manufacturing. In Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (Vol. 1992-October, pp. 76–83). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/BIPOL.1992.274079
Register to see more suggestions
Mendeley helps you to discover research relevant for your work.
