The paper discusses the design process of a programmable logic controller implemented by means of FPGA device. Designed PLC is to be compliant with EN 61131-3 standard. Different aspects of instruction list and hardware architecture designing are presented, e.g. PLC structure with particular emphasis on central processing unit or memory map. Conclusions on an EN 61131-3 Standard are also shown. The developed PLC is implemented using FPGA device. This gives opportunity to develop interesting solutions. For example, using dual port RAM gives us opportunity to develop bit/word access without necessity of masking bits. Up to date FPGA devices have also disadvantage-there are no tri-state buffers inside. This is the reason for using multiplexers that control traffic on busses.
Chmiel, M., Czerwinski, R., & Smolarek, P. (2015). IEC 61131-3-based PLC implemented by means of FPGA. In IFAC-PapersOnLine (Vol. 28, pp. 374–379). https://doi.org/10.1016/j.ifacol.2015.07.063