Design of efficient approximate compressor for digital image processing

Abstract

For various error tolerant applications like multimedia and signal processing, approximate computing is the most suited computing technique. With the cost of accuracy, approximate computing gives us faster and efficient results with possibly low power consumption. A new approach and design towards optimizing the partial products reduction stage of a compressor-based multiplier have been introduced in this paper. Two new designs of 4:2 compressors and six new designs of approximate multipliers using the approximate compressors have been proposed. The results of the simulation of the proposed designs show that there has been a significant improvement in the accuracy with reduction in power and time consumption when we compare to the previous approximate designs. An image processing application is used to prove the efficiency of the proposed designs.