A Practical FPGA-Based Architecture for Arbitrary-Ratio Sample Rate Conversion

Abstract

Many digital systems for telecommunications are implemented via the Software Defined Radio technique today. In such systems, digitally implemented modules to interface analog-to-digital converters with the rest of the system working at a different clock rate can be required. When implementing these modules, generated spurious harmonics and limited hardware resource problems can be critical factors in embedded applications. The article describes a Field-Programmable Gate Array (FPGA) circuit for arbitrary-ratio re-sampling of signals in the Low Frequency to Very High Frequency bands, intended for Software Defined Radio applications. The proposed resampler allows to control Spurious Free Dynamic Range while providing a simple, practical interface between the input and output clock domains that requires no additional clock, thus making it appropriate for FPGA clock-limited designs. Both up-sampling and down-sampling variants are presented. Resource utilization for FPGA implementations is also discussed.