A switching frequency optimized space vector pulse width modulation (SVPWM) scheme for cascaded multilevel inverters

Abstract

This paper presents a novel switching frequency optimized space vector pulse width modulation (SVPWM) scheme for cascaded multilevel inverters. The proposed SVPWM is developed in a α′β′ coordinate system, in which the voltage vectors have only integer entries and the absolute increment of coordinate values between adjacent vectors is equal to dc-bus voltage of power cells (1 pu). The new SVPWM scheme is built with three categories of switching paths. During each switching path, the change of one phase voltage is limited in 1 pu. This contributes to decrease the number of commutations of switches. The proposed SVPWM scheme is validated on a 7-level cascaded inverter and the results show that it significantly outperforms traditional SVPWM schemes in terms of decreasing the number of switch commutations.