Low-Power-Delay-Product radix-4 8∗8 Booth multiplier in CMOS

Abstract

The quest continues for microelectronic implementations with higher throughput and reduced power consumption, particularly for digital signal processing, graphic processing unit and CPU portable applications. This Letter focuses on the digital multiplier circuit, which is a key component in determining the power-delay-product for numerous battery powered applications. A proposed radix-4 8×8 Booth multiplier is implemented using four stages with a unique optimised stage-1 architecture. Instead of using adder/subtractor in stage-1, it is replaced with a novel binary-to-2's complement converter and a 2:1 MUX to reduce the delay and power consumption by 7.08 and 49.46%, respectively, compared to the other stages. The proposed design is implemented using CMOS 90 nm technology with 1.2 V supply to demonstrate performance.