Leakage power reduction using the body bias and pin reordering technique

Abstract

This paper presents a new method to reduce the standby leakage power consumption using the body bias and pin reordering technique for nanometer-scale CMOS circuits. The proposed method, unlike the conventional reverse body biasing (RBB) technique, considers gate leakage to minimize the negative effects of the existing RBB approach. This minimization of the negative effects can be achieved by intelligently applying proper body bias to the appropriate CMOS network based on its status (on-/off-state) with the aid of a pin reordering technique. Experimental results on ISCAS’85 benchmark circuits show that the proposed method can achieve improvements in terms of leakage power savings that range from 16% to 38% when compared with the previous works.